From d6bd4ea35437b1d39933e9526779e8c6e03125e0 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland@gmail.com>
Date: Fri, 5 May 2023 08:17:41 -0700
Subject: [PATCH] Revert "[RISCV] Add sifive-x280 processor with all of its
 extensions"

This commit causes tests to fail.

This reverts commit 55e196e7718c543b4492f2949c13de003a4ba443.
---
 clang/test/Driver/riscv-cpus.c           | 14 --------------
 llvm/docs/ReleaseNotes.rst               |  1 -
 llvm/lib/Target/RISCV/RISCVProcessors.td | 16 ----------------
 3 files changed, 31 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index a484b07..7632531 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -167,20 +167,6 @@
 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76"
 
-// mcpu with default march include experimental extensions
-// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-x280 | FileCheck -check-prefix=MCPU-SIFIVE-X280 %s
-// MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" "+zvl32b"
-// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b"
-// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
-
 // Check failed cases
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 845cee9..c764a50 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -175,7 +175,6 @@ Changes to the RISC-V Backend
   ``RISCV::parseCPU``. The ``CPUKind`` enum is no longer part of the
   RISCVTargetParser.h interface. Similar for ``parseTuneCPUkind`` and
   ``checkTuneCPUKind``.
-* Add sifive-x280 processor.
 
 Changes to the WebAssembly Backend
 ----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 69edacc..67b0364 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -166,22 +166,6 @@ def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
                                       FeatureStdExtC],
                                      [TuneSiFive7]>;
 
-def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
-                                      [Feature64Bit,
-                                       FeatureStdExtZifencei,
-                                       FeatureStdExtM,
-                                       FeatureStdExtA,
-                                       FeatureStdExtF,
-                                       FeatureStdExtD,
-                                       FeatureStdExtC,
-                                       FeatureStdExtV,
-                                       FeatureStdExtZvl512b,
-                                       FeatureStdExtZfh,
-                                       FeatureStdExtZvfh,
-                                       FeatureStdExtZba,
-                                       FeatureStdExtZbb],
-                                      [TuneSiFive7]>;
-
 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
                                               SyntacoreSCR1Model,
                                               [Feature32Bit,
-- 
2.7.4