From d6a8a0798f75d26caa3f49000aa7ab25a6dd354a Mon Sep 17 00:00:00 2001 From: David Sherwood Date: Wed, 19 Oct 2022 11:53:21 +0000 Subject: [PATCH] [AArch64][SVE2] Add the SVE2.1 bfmlslb and bfmlslt instructions This patch adds the assembly/disassembly for the following instructions: BFMLSLB : BFloat16 floating-point multiply-subtract long from single-precision (bottom) BFMLSLT : BFloat16 floating-point multiply-subtract long from single-precision (top) Both the vector and indexed forms are added for each. The reference can be found here: https://developer.arm.com/documentation/ddi0602/2022-09 Differential Revision: https://reviews.llvm.org/D136439 --- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 12 ++-- llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td | 2 +- llvm/lib/Target/AArch64/SVEInstrFormats.td | 16 +++-- llvm/test/MC/AArch64/SVE2p1/bfmlslb-diagnostics.s | 37 +++++++++++ llvm/test/MC/AArch64/SVE2p1/bfmlslb.s | 78 +++++++++++++++++++++++ llvm/test/MC/AArch64/SVE2p1/bfmlslt-diagnostics.s | 37 +++++++++++ llvm/test/MC/AArch64/SVE2p1/bfmlslt.s | 78 +++++++++++++++++++++++ 7 files changed, 248 insertions(+), 12 deletions(-) create mode 100644 llvm/test/MC/AArch64/SVE2p1/bfmlslb-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE2p1/bfmlslb.s create mode 100644 llvm/test/MC/AArch64/SVE2p1/bfmlslt-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE2p1/bfmlslt.s diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index b25c90b..e1c029f 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -2118,10 +2118,10 @@ let Predicates = [HasBF16, HasSVE] in { } // End HasBF16, HasSVE let Predicates = [HasBF16, HasSVEorSME] in { - defm BFMLALB_ZZZ : sve_bfloat_matmul_longvecl<0b0, "bfmlalb", int_aarch64_sve_bfmlalb>; - defm BFMLALT_ZZZ : sve_bfloat_matmul_longvecl<0b1, "bfmlalt", int_aarch64_sve_bfmlalt>; - defm BFMLALB_ZZI : sve_bfloat_matmul_longvecl_idx<0b0, "bfmlalb", int_aarch64_sve_bfmlalb_lane>; - defm BFMLALT_ZZI : sve_bfloat_matmul_longvecl_idx<0b1, "bfmlalt", int_aarch64_sve_bfmlalt_lane>; + defm BFMLALB_ZZZ : sve_bfloat_matmul_longvecl<0b0, 0b0, "bfmlalb", int_aarch64_sve_bfmlalb>; + defm BFMLALT_ZZZ : sve_bfloat_matmul_longvecl<0b1, 0b0, "bfmlalt", int_aarch64_sve_bfmlalt>; + defm BFMLALB_ZZZI : sve_bfloat_matmul_longvecl_idx<0b0, 0b0, "bfmlalb", int_aarch64_sve_bfmlalb_lane>; + defm BFMLALT_ZZZI : sve_bfloat_matmul_longvecl_idx<0b1, 0b0, "bfmlalt", int_aarch64_sve_bfmlalt_lane>; defm BFCVT_ZPmZ : sve_bfloat_convert<0b1, "bfcvt", int_aarch64_sve_fcvt_bf16f32>; defm BFCVTNT_ZPmZ : sve_bfloat_convert<0b0, "bfcvtnt", int_aarch64_sve_fcvtnt_bf16f32>; } // End HasBF16, HasSVEorSME @@ -3577,4 +3577,8 @@ let Predicates = [HasSVE2p1_or_HasSME2] in { defm FCLAMP_ZZZ : sve2p1_fclamp<"fclamp">; def FDOT_ZZZ_S : sve_float_dot<0b0, "fdot">; def FDOT_ZZZI_S : sve_float_dot_indexed<0b0, "fdot">; +def BFMLSLB_ZZZ_S : sve_bfloat_matmul_longvecl<0b0, 0b1, "bfmlslb">; +def BFMLSLT_ZZZ_S : sve_bfloat_matmul_longvecl<0b1, 0b1, "bfmlslt">; +def BFMLSLB_ZZZI_S : sve_bfloat_matmul_longvecl_idx<0b0, 0b1, "bfmlslb">; +def BFMLSLT_ZZZI_S : sve_bfloat_matmul_longvecl_idx<0b1, 0b1, "bfmlslt">; } // End HasSVE2p1_or_HasSME2 diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td index eb5b971..c472de8 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td +++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td @@ -2048,7 +2048,7 @@ def : InstRW<[N2Write_4cyc_1V], (instrs BFDOT_ZZI, BFDOT_ZZZ)>; def : InstRW<[N2Write_5cyc_1V], (instrs BFMMLA_ZZZ)>; // Multiply accumulate long -def : InstRW<[N2Write_4cyc_1V], (instregex "^BFMLAL[BT]_ZZ[ZI]$")>; +def : InstRW<[N2Write_4cyc_1V], (instregex "^BFMLAL[BT]_ZZZ(I)?$")>; // SVE Load instructions // ----------------------------------------------------------------------------- diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 32507d03..d81bfac 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -8272,19 +8272,20 @@ multiclass sve_bfloat_matmul { def : SVE_3_Op_Pat(NAME)>; } -class sve_bfloat_matmul_longvecl +class sve_bfloat_matmul_longvecl : sve_bfloat_matmul { let Inst{23} = 0b1; - let Inst{14-13} = 0b00; + let Inst{14} = 0b0; + let Inst{13} = sub; let Inst{10} = BT; } -multiclass sve_bfloat_matmul_longvecl { - def NAME : sve_bfloat_matmul_longvecl; +multiclass sve_bfloat_matmul_longvecl { + def NAME : sve_bfloat_matmul_longvecl; def : SVE_3_Op_Pat(NAME)>; } -class sve_bfloat_matmul_longvecl_idx +class sve_bfloat_matmul_longvecl_idx : sve_bfloat_dot_base<0b01, asm, "\t$Zda, $Zn, $Zm$iop", (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm, VectorIndexH:$iop)> { bits<3> iop; @@ -8292,12 +8293,13 @@ class sve_bfloat_matmul_longvecl_idx let Inst{23} = 0b1; let Inst{20-19} = iop{2-1}; let Inst{18-16} = Zm; + let Inst{13} = sub; let Inst{11} = iop{0}; let Inst{10} = BT; } -multiclass sve_bfloat_matmul_longvecl_idx { - def NAME : sve_bfloat_matmul_longvecl_idx; +multiclass sve_bfloat_matmul_longvecl_idx { + def NAME : sve_bfloat_matmul_longvecl_idx; def : SVE_4_Op_Imm_Pat(NAME)>; } diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmlslb-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/bfmlslb-diagnostics.s new file mode 100644 index 0000000..30e48c2 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p1/bfmlslb-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector lane index + +bfmlslb z0.s, z0.h, z0.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: bfmlslb z0.s, z0.h, z0.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmlslb z0.s, z0.h, z0.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: bfmlslb z0.s, z0.h, z0.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmlslb z0.s, z0.h, z8.h[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfmlslb z0.s, z0.h, z8.h[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector suffix + +bfmlslb z0.s, z0.s, z0.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfmlslb z0.s, z0.s, z0.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmlslb z23.d, z23.h, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfmlslb z23.d, z23.h, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmlslb z23.d, z23.h, z13.h[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfmlslb z23.d, z23.h, z13.h[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmlslb.s b/llvm/test/MC/AArch64/SVE2p1/bfmlslb.s new file mode 100644 index 0000000..b110983 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p1/bfmlslb.s @@ -0,0 +1,78 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +movprfx z23, z31 +bfmlslb z23.s, z13.h, z8.h // 01100100-11101000-10100001-10110111 +// CHECK-INST: movprfx z23, z31 +// CHECK-INST: bfmlslb z23.s, z13.h, z8.h +// CHECK-ENCODING: [0xb7,0xa1,0xe8,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64e8a1b7 + +bfmlslb z0.s, z0.h, z0.h // 01100100-11100000-10100000-00000000 +// CHECK-INST: bfmlslb z0.s, z0.h, z0.h +// CHECK-ENCODING: [0x00,0xa0,0xe0,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64e0a000 + +bfmlslb z21.s, z10.h, z21.h // 01100100-11110101-10100001-01010101 +// CHECK-INST: bfmlslb z21.s, z10.h, z21.h +// CHECK-ENCODING: [0x55,0xa1,0xf5,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64f5a155 + +bfmlslb z23.s, z13.h, z8.h // 01100100-11101000-10100001-10110111 +// CHECK-INST: bfmlslb z23.s, z13.h, z8.h +// CHECK-ENCODING: [0xb7,0xa1,0xe8,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64e8a1b7 + +bfmlslb z31.s, z31.h, z31.h // 01100100-11111111-10100011-11111111 +// CHECK-INST: bfmlslb z31.s, z31.h, z31.h +// CHECK-ENCODING: [0xff,0xa3,0xff,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64ffa3ff + +movprfx z23, z31 +bfmlslb z23.s, z13.h, z0.h[3] // 01100100-11101000-01101001-10110111 +// CHECK-INST: movprfx z23, z31 +// CHECK-INST: bfmlslb z23.s, z13.h, z0.h[3] +// CHECK-ENCODING: [0xb7,0x69,0xe8,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64e869b7 + +bfmlslb z0.s, z0.h, z0.h[0] // 01100100-11100000-01100000-00000000 +// CHECK-INST: bfmlslb z0.s, z0.h, z0.h[0] +// CHECK-ENCODING: [0x00,0x60,0xe0,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64e06000 + +bfmlslb z21.s, z10.h, z5.h[4] // 01100100-11110101-01100001-01010101 +// CHECK-INST: bfmlslb z21.s, z10.h, z5.h[4] +// CHECK-ENCODING: [0x55,0x61,0xf5,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64f56155 + +bfmlslb z23.s, z13.h, z0.h[3] // 01100100-11101000-01101001-10110111 +// CHECK-INST: bfmlslb z23.s, z13.h, z0.h[3] +// CHECK-ENCODING: [0xb7,0x69,0xe8,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64e869b7 + +bfmlslb z31.s, z31.h, z7.h[7] // 01100100-11111111-01101011-11111111 +// CHECK-INST: bfmlslb z31.s, z31.h, z7.h[7] +// CHECK-ENCODING: [0xff,0x6b,0xff,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64ff6bff diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmlslt-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/bfmlslt-diagnostics.s new file mode 100644 index 0000000..fc04a5f --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p1/bfmlslt-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector lane index + +bfmlslt z0.s, z0.h, z0.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: bfmlslt z0.s, z0.h, z0.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmlslt z0.s, z0.h, z0.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: bfmlslt z0.s, z0.h, z0.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmlslt z0.s, z0.h, z8.h[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfmlslt z0.s, z0.h, z8.h[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector suffix + +bfmlslt z0.s, z0.s, z0.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfmlslt z0.s, z0.s, z0.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmlslt z23.d, z23.h, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfmlslt z23.d, z23.h, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmlslt z23.d, z23.h, z13.h[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfmlslt z23.d, z23.h, z13.h[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p1/bfmlslt.s b/llvm/test/MC/AArch64/SVE2p1/bfmlslt.s new file mode 100644 index 0000000..bbb8b15 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p1/bfmlslt.s @@ -0,0 +1,78 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +movprfx z23, z31 +bfmlslt z23.s, z13.h, z8.h // 01100100-11101000-10100101-10110111 +// CHECK-INST: movprfx z23, z31 +// CHECK-INST: bfmlslt z23.s, z13.h, z8.h +// CHECK-ENCODING: [0xb7,0xa5,0xe8,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64e8a5b7 + +bfmlslt z0.s, z0.h, z0.h // 01100100-11100000-10100100-00000000 +// CHECK-INST: bfmlslt z0.s, z0.h, z0.h +// CHECK-ENCODING: [0x00,0xa4,0xe0,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64e0a400 + +bfmlslt z21.s, z10.h, z21.h // 01100100-11110101-10100101-01010101 +// CHECK-INST: bfmlslt z21.s, z10.h, z21.h +// CHECK-ENCODING: [0x55,0xa5,0xf5,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64f5a555 + +bfmlslt z23.s, z13.h, z8.h // 01100100-11101000-10100101-10110111 +// CHECK-INST: bfmlslt z23.s, z13.h, z8.h +// CHECK-ENCODING: [0xb7,0xa5,0xe8,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64e8a5b7 + +bfmlslt z31.s, z31.h, z31.h // 01100100-11111111-10100111-11111111 +// CHECK-INST: bfmlslt z31.s, z31.h, z31.h +// CHECK-ENCODING: [0xff,0xa7,0xff,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64ffa7ff + +movprfx z23, z31 +bfmlslt z23.s, z13.h, z0.h[3] // 01100100-11101000-01101101-10110111 +// CHECK-INST: movprfx z23, z31 +// CHECK-INST: bfmlslt z23.s, z13.h, z0.h[3] +// CHECK-ENCODING: [0xb7,0x6d,0xe8,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64e86db7 + +bfmlslt z0.s, z0.h, z0.h[0] // 01100100-11100000-01100100-00000000 +// CHECK-INST: bfmlslt z0.s, z0.h, z0.h[0] +// CHECK-ENCODING: [0x00,0x64,0xe0,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64e06400 + +bfmlslt z21.s, z10.h, z5.h[4] // 01100100-11110101-01100101-01010101 +// CHECK-INST: bfmlslt z21.s, z10.h, z5.h[4] +// CHECK-ENCODING: [0x55,0x65,0xf5,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64f56555 + +bfmlslt z23.s, z13.h, z0.h[3] // 01100100-11101000-01101101-10110111 +// CHECK-INST: bfmlslt z23.s, z13.h, z0.h[3] +// CHECK-ENCODING: [0xb7,0x6d,0xe8,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64e86db7 + +bfmlslt z31.s, z31.h, z7.h[7] // 01100100-11111111-01101111-11111111 +// CHECK-INST: bfmlslt z31.s, z31.h, z7.h[7] +// CHECK-ENCODING: [0xff,0x6f,0xff,0x64] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: 64ff6fff -- 2.7.4