From d65438d0ca7cf1e03a27767dbf2e455ac0b9b154 Mon Sep 17 00:00:00 2001 From: Francis Visoiu Mistrih Date: Thu, 8 Feb 2018 23:42:27 +0000 Subject: [PATCH] [CodeGen] Move printing '\n' from MachineInstr::print to MachineBasicBlock::print MBB.print wasn't printing it, but the MIRPrinter is printing it. The goal is to unify that as much as possible. llvm-svn: 324681 --- llvm/lib/CodeGen/MachineBasicBlock.cpp | 1 + llvm/lib/CodeGen/MachineInstr.cpp | 2 -- llvm/lib/CodeGen/MachineScheduler.cpp | 17 +++++++---- llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | 1 + llvm/lib/Target/AArch64/AArch64CollectLOH.cpp | 44 +++++++++++++++++---------- 5 files changed, 41 insertions(+), 24 deletions(-) diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp index 7da604c..1076c19 100644 --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -352,6 +352,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST, if (I.isInsideBundle()) OS << " * "; I.print(OS, MST, IsStandalone); + OS << '\n'; } // Print the successors of this block according to the CFG. diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index d2d3bc7..80665b5 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -1473,8 +1473,6 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, if (isIndirectDebugValue()) OS << " indirect"; } - - OS << '\n'; } bool MachineInstr::addRegisterKilled(unsigned IncomingReg, diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index f37479e..c0a4f65 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -549,9 +549,13 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler, } DEBUG(dbgs() << "********** MI Scheduling **********\n"); DEBUG(dbgs() << MF->getName() << ":" << printMBBReference(*MBB) << " " - << MBB->getName() << "\n From: " << *I << " To: "; - if (RegionEnd != MBB->end()) dbgs() << *RegionEnd; - else dbgs() << "End"; + << MBB->getName() << "\n From: " << *I << '\n' + << " To: "; + if (RegionEnd != MBB->end()) { + dbgs() << *RegionEnd << '\n'; + } else { + dbgs() << "End"; + } dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n'); if (DumpCriticalPathLength) { errs() << MF->getName(); @@ -1133,7 +1137,7 @@ void ScheduleDAGMILive::updatePressureDiffs( DEBUG( dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") " << printReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask) - << ' ' << *SU.getInstr(); + << ' ' << *SU.getInstr() << '\n'; dbgs() << " to "; PDiff.dump(*TRI); ); @@ -1170,7 +1174,7 @@ void ScheduleDAGMILive::updatePressureDiffs( PDiff.addPressureChange(Reg, true, &MRI); DEBUG( dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") " - << *SU->getInstr(); + << *SU->getInstr() << '\n'; dbgs() << " to "; PDiff.dump(*TRI); ); @@ -3334,7 +3338,8 @@ SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) { IsTopNode = true; Top.removeReady(SU); - DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr()); + DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr() + << '\n'); return SU; } diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp index 9249fa8..3afa78d 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -1099,6 +1099,7 @@ void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const { // Cannot completely remove virtual function even in release mode. #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) SU->getInstr()->dump(); + dbgs() << '\n'; #endif } diff --git a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp index 0a9167e..baa1b0e 100644 --- a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp +++ b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp @@ -380,8 +380,9 @@ static bool handleMiddleInst(const MachineInstr &MI, LOHInfo &DefInfo, static void handleADRP(const MachineInstr &MI, AArch64FunctionInfo &AFI, LOHInfo &Info) { if (Info.LastADRP != nullptr) { - DEBUG(dbgs() << "Adding MCLOH_AdrpAdrp:\n" << '\t' << MI << '\t' - << *Info.LastADRP); + DEBUG(dbgs() << "Adding MCLOH_AdrpAdrp:\n" + << '\t' << MI << '\n' + << '\t' << *Info.LastADRP << '\n'); AFI.addLOHDirective(MCLOH_AdrpAdrp, {&MI, Info.LastADRP}); ++NumADRPSimpleCandidate; } @@ -390,48 +391,59 @@ static void handleADRP(const MachineInstr &MI, AArch64FunctionInfo &AFI, if (Info.IsCandidate) { switch (Info.Type) { case MCLOH_AdrpAdd: - DEBUG(dbgs() << "Adding MCLOH_AdrpAdd:\n" << '\t' << MI << '\t' - << *Info.MI0); + DEBUG(dbgs() << "Adding MCLOH_AdrpAdd:\n" + << '\t' << MI << '\n' + << '\t' << *Info.MI0 << '\n'); AFI.addLOHDirective(MCLOH_AdrpAdd, {&MI, Info.MI0}); ++NumADRSimpleCandidate; break; case MCLOH_AdrpLdr: if (supportLoadFromLiteral(*Info.MI0)) { - DEBUG(dbgs() << "Adding MCLOH_AdrpLdr:\n" << '\t' << MI << '\t' - << *Info.MI0); + DEBUG(dbgs() << "Adding MCLOH_AdrpLdr:\n" + << '\t' << MI << '\n' + << '\t' << *Info.MI0 << '\n'); AFI.addLOHDirective(MCLOH_AdrpLdr, {&MI, Info.MI0}); ++NumADRPToLDR; } break; case MCLOH_AdrpAddLdr: - DEBUG(dbgs() << "Adding MCLOH_AdrpAddLdr:\n" << '\t' << MI << '\t' - << *Info.MI1 << '\t' << *Info.MI0); + DEBUG(dbgs() << "Adding MCLOH_AdrpAddLdr:\n" + << '\t' << MI << '\n' + << '\t' << *Info.MI1 << '\n' + << '\t' << *Info.MI0 << '\n'); AFI.addLOHDirective(MCLOH_AdrpAddLdr, {&MI, Info.MI1, Info.MI0}); ++NumADDToLDR; break; case MCLOH_AdrpAddStr: if (Info.MI1 != nullptr) { - DEBUG(dbgs() << "Adding MCLOH_AdrpAddStr:\n" << '\t' << MI << '\t' - << *Info.MI1 << '\t' << *Info.MI0); + DEBUG(dbgs() << "Adding MCLOH_AdrpAddStr:\n" + << '\t' << MI << '\n' + << '\t' << *Info.MI1 << '\n' + << '\t' << *Info.MI0 << '\n'); AFI.addLOHDirective(MCLOH_AdrpAddStr, {&MI, Info.MI1, Info.MI0}); ++NumADDToSTR; } break; case MCLOH_AdrpLdrGotLdr: - DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotLdr:\n" << '\t' << MI << '\t' - << *Info.MI1 << '\t' << *Info.MI0); + DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotLdr:\n" + << '\t' << MI << '\n' + << '\t' << *Info.MI1 << '\n' + << '\t' << *Info.MI0 << '\n'); AFI.addLOHDirective(MCLOH_AdrpLdrGotLdr, {&MI, Info.MI1, Info.MI0}); ++NumLDRToLDR; break; case MCLOH_AdrpLdrGotStr: - DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotStr:\n" << '\t' << MI << '\t' - << *Info.MI1 << '\t' << *Info.MI0); + DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotStr:\n" + << '\t' << MI << '\n' + << '\t' << *Info.MI1 << '\n' + << '\t' << *Info.MI0 << '\n'); AFI.addLOHDirective(MCLOH_AdrpLdrGotStr, {&MI, Info.MI1, Info.MI0}); ++NumLDRToSTR; break; case MCLOH_AdrpLdrGot: - DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGot:\n" << '\t' << MI << '\t' - << *Info.MI0); + DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGot:\n" + << '\t' << MI << '\n' + << '\t' << *Info.MI0 << '\n'); AFI.addLOHDirective(MCLOH_AdrpLdrGot, {&MI, Info.MI0}); break; case MCLOH_AdrpAdrp: -- 2.7.4