From d63ef93b4b20b4b6b0f02e1c030160564ff40dbd Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Fri, 19 Dec 2014 19:51:35 +0000 Subject: [PATCH] [Hexagon] Adding more xtype shift instructions. llvm-svn: 224608 --- llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 107 ++++++++++++++++++++++ llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt | 2 + llvm/test/MC/Disassembler/Hexagon/xtype_shift.txt | 20 ++++ 3 files changed, 129 insertions(+) diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index be7e3da..678c87d 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -4478,6 +4478,113 @@ defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>; defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>; } +//===----------------------------------------------------------------------===// +let hasSideEffects = 0 in +class T_S3op_1 MajOp, bits<3> MinOp, + bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0> + : SInst <(outs RC:$dst), + (ins DoubleRegs:$src1, DoubleRegs:$src2), + "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "") + #!if(hasShift,":>>1","") + #!if(isSat, ":sat", ""), + [], "", S_3op_tc_2_SLOT23 > { + bits<5> dst; + bits<5> src1; + bits<5> src2; + + let IClass = 0b1100; + + let Inst{27-24} = 0b0001; + let Inst{23-22} = MajOp; + let Inst{20-16} = !if (SwapOps, src2, src1); + let Inst{12-8} = !if (SwapOps, src1, src2); + let Inst{7-5} = MinOp; + let Inst{4-0} = dst; + } + +class T_S3op_64 MajOp, bits<3> MinOp, bit SwapOps, + bit isSat = 0, bit isRnd = 0, bit hasShift = 0 > + : T_S3op_1 ; + +let isCodeGenOnly = 0 in +def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>; + +//===----------------------------------------------------------------------===// +// Template class used by vector shift, vector rotate, vector neg, +// 32-bit shift, 64-bit shifts, etc. +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0 in +class T_S3op_3 MajOp, + bits<2> MinOp, bit isSat = 0, list pattern = [] > + : SInst <(outs RC:$dst), + (ins RC:$src1, IntRegs:$src2), + "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""), + pattern, "", S_3op_tc_1_SLOT23> { + bits<5> dst; + bits<5> src1; + bits<5> src2; + + let IClass = 0b1100; + + let Inst{27-24} = !if(!eq(!cast(RC), "IntRegs"), 0b0110, 0b0011); + let Inst{23-22} = MajOp; + let Inst{20-16} = src1; + let Inst{12-8} = src2; + let Inst{7-6} = MinOp; + let Inst{4-0} = dst; + } + +let hasNewValue = 1 in +class T_S3op_shift32 MinOp> + : T_S3op_3 ; + +let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in +class T_S3op_shift32_Sat MinOp> + : T_S3op_3 ; + + +class T_S3op_shift64 MinOp> + : T_S3op_3 ; + + +class T_S3op_shiftVect MajOp, bits<2> MinOp> + : T_S3op_3 ; + + +// Shift by register +// Rdd=[asr|lsr|asl|lsl](Rss,Rt) + +let isCodeGenOnly = 0 in { +def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>; +def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>; +def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>; +def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>; +} + +// Rd=[asr|lsr|asl|lsl](Rs,Rt) + +let isCodeGenOnly = 0 in { +def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>; +def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>; +def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>; +def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>; +} + +// Shift by register with saturation +// Rd=asr(Rs,Rt):sat +// Rd=asl(Rs,Rt):sat + +let Defs = [USR_OVF], isCodeGenOnly = 0 in { + def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>; + def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>; +} + // Multi-class for logical operators : // Shift by immediate/register and accumulate/logical multiclass xtype_imm { diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt index d4a10cf..0ac3e8b 100644 --- a/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt @@ -22,6 +22,8 @@ # CHECK: r17:16 = deinterleave(r21:20) 0xb0 0xc0 0xd4 0x80 # CHECK: r17:16 = interleave(r21:20) +0xd0 0xde 0x94 0xc1 +# CHECK: r17:16 = lfs(r21:20, r31:30) 0x11 0xde 0x14 0xd0 # CHECK: r17 = parity(r21:20, r31:30) 0x11 0xdf 0xd5 0x8c diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_shift.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_shift.txt index 51cbb89..f18407a 100644 --- a/llvm/test/MC/Disassembler/Hexagon/xtype_shift.txt +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_shift.txt @@ -74,6 +74,22 @@ # CHECK: r17 = asr(r21, #31):rnd 0x51 0xdf 0x55 0x8c # CHECK: r17 = asl(r21, #31):sat +0x10 0xdf 0x94 0xc3 +# CHECK: r17:16 = asr(r21:20, r31) +0x50 0xdf 0x94 0xc3 +# CHECK: r17:16 = lsr(r21:20, r31) +0x90 0xdf 0x94 0xc3 +# CHECK: r17:16 = asl(r21:20, r31) +0xd0 0xdf 0x94 0xc3 +# CHECK: r17:16 = lsl(r21:20, r31) +0x11 0xdf 0x55 0xc6 +# CHECK: r17 = asr(r21, r31) +0x51 0xdf 0x55 0xc6 +# CHECK: r17 = lsr(r21, r31) +0x91 0xdf 0x55 0xc6 +# CHECK: r17 = asl(r21, r31) +0xd1 0xdf 0x55 0xc6 +# CHECK: r17 = lsl(r21, r31) 0x10 0xdf 0x94 0xcb # CHECK: r17:16 -= asr(r21:20, r31) 0x50 0xdf 0x94 0xcb @@ -146,3 +162,7 @@ # CHECK: r17 &= asl(r21, r31) 0xd1 0xdf 0x55 0xcc # CHECK: r17 &= lsl(r21, r31) +0x11 0xdf 0x15 0xc6 +# CHECK: r17 = asr(r21, r31):sat +0x91 0xdf 0x15 0xc6 +# CHECK: r17 = asl(r21, r31):sat -- 2.7.4