From d632e864351ac3df3ab4bb224ba27b0634ce93be Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 27 Sep 2022 19:24:21 +0300 Subject: [PATCH] pwm: lpss: Add a comment to the bypass field MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Add a comment to the bypass field based on the commit b997e3edca4f ("pwm: lpss: Set enable-bit before waiting for update-bit to go low"). Signed-off-by: Andy Shevchenko Reviewed-by: Hans de Goede Acked-by: Uwe Kleine-König Signed-off-by: Thierry Reding --- drivers/pwm/pwm-lpss.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h index c344921..8e82eb5 100644 --- a/drivers/pwm/pwm-lpss.h +++ b/drivers/pwm/pwm-lpss.h @@ -25,6 +25,11 @@ struct pwm_lpss_boardinfo { unsigned long clk_rate; unsigned int npwm; unsigned long base_unit_bits; + /* + * Some versions of the IP may stuck in the state machine if enable + * bit is not set, and hence update bit will show busy status till + * the reset. For the rest it may be otherwise. + */ bool bypass; /* * On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device -- 2.7.4