From d61e4ba33e254ef8df33c355ba1b2865e3885693 Mon Sep 17 00:00:00 2001 From: Derek Lai Date: Tue, 2 Aug 2022 13:47:03 +0800 Subject: [PATCH] drm/amd/display: do not change pipe split policy for RV2 [Why] RV2 do not change pipe split policy in the minimal pipe split transition state. This will unblock mode support on some parts that limit to DPM0 for power reason. [How] Do not change pipe split policy in the minimal pipe split transition state to allow 4k multi display configs to be supported at DPM0. Reviewed-by: Charlene Liu Acked-by: Brian Chang Signed-off-by: Derek Lai Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 9 ++++-- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 18 ++++++++++++ .../gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c | 32 ++++------------------ 4 files changed, 31 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 0fade2f..5006263 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3546,8 +3546,10 @@ static bool commit_minimal_transition_state(struct dc *dc, if (!transition_context) return false; - tmp_policy = dc->debug.pipe_split_policy; - dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; + if (!dc->config.is_vmin_only_asic) { + tmp_policy = dc->debug.pipe_split_policy; + dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; + } dc_resource_state_copy_construct(transition_base_context, transition_context); @@ -3573,7 +3575,8 @@ static bool commit_minimal_transition_state(struct dc *dc, dc_release_state(transition_context); //restore previous pipe split policy - dc->debug.pipe_split_policy = tmp_policy; + if (!dc->config.is_vmin_only_asic) + dc->debug.pipe_split_policy = tmp_policy; if (ret != DC_OK) { //this should never happen diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 2f2d009..322ecc9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -401,6 +401,7 @@ struct dc_config { uint8_t vblank_alignment_max_frame_time_diff; bool is_asymmetric_memory; bool is_single_rank_dimm; + bool is_vmin_only_asic; bool use_pipe_ctx_sync_logic; bool ignore_dpref_ss; bool enable_mipi_converter_optimization; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 174eebb..831080b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1495,6 +1495,24 @@ static bool dcn10_resource_construct( /* Other architectures we build for build this with soft-float */ dcn10_resource_construct_fp(dc); + if (!dc->config.is_vmin_only_asic) + if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev)) + switch (dc->ctx->asic_id.pci_revision_id) { + case PRID_DALI_DE: + case PRID_DALI_DF: + case PRID_DALI_E3: + case PRID_DALI_E4: + case PRID_POLLOCK_94: + case PRID_POLLOCK_95: + case PRID_POLLOCK_E9: + case PRID_POLLOCK_EA: + case PRID_POLLOCK_EB: + dc->config.is_vmin_only_asic = true; + break; + default: + break; + } + pool->base.pp_smu = dcn10_pp_smu_create(ctx); /* diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c index db3b16b..d46adc8 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c @@ -736,30 +736,13 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v, hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz); } -static unsigned int get_highest_allowed_voltage_level(uint32_t chip_family, - uint32_t hw_internal_rev, - uint32_t pci_revision_id) +static unsigned int get_highest_allowed_voltage_level(bool is_vmin_only_asic) { /* for low power RV2 variants, the highest voltage level we want is 0 */ - if ((chip_family == FAMILY_RV) && - ASICREV_IS_RAVEN2(hw_internal_rev)) - switch (pci_revision_id) { - case PRID_DALI_DE: - case PRID_DALI_DF: - case PRID_DALI_E3: - case PRID_DALI_E4: - case PRID_POLLOCK_94: - case PRID_POLLOCK_95: - case PRID_POLLOCK_E9: - case PRID_POLLOCK_EA: - case PRID_POLLOCK_EB: - return 0; - default: - break; - } - - /* we are ok with all levels */ - return 4; + if (is_vmin_only_asic) + return 0; + else /* we are ok with all levels */ + return 4; } bool dcn_validate_bandwidth( @@ -1323,10 +1306,7 @@ bool dcn_validate_bandwidth( PERFORMANCE_TRACE_END(); BW_VAL_TRACE_FINISH(); - if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level( - dc->ctx->asic_id.chip_family, - dc->ctx->asic_id.hw_internal_rev, - dc->ctx->asic_id.pci_revision_id)) + if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic)) return true; else return false; -- 2.7.4