From d607b9684b188d020a00e9cfaa502b782f29d538 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Thu, 1 Nov 2012 08:20:23 +0000 Subject: [PATCH] powerpc/85xx: implement check for erratum A-004580 work-around The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: Timur Tabi Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 48 +++++++++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + arch/powerpc/include/asm/immap_85xx.h | 2 +- 3 files changed, 50 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index ccfad56..7d38e1c 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -24,6 +24,7 @@ #include #include #include +#include "fsl_corenet_serdes.h" #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 /* @@ -84,6 +85,49 @@ static void check_erratum_a4849(uint32_t svr) } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004580 +/* + * This work-around is implemented in PBI, so just check to see if the + * work-around was actually applied. To do this, we check for specific data + * at specific addresses in the SerDes register block. + * + * The work-around says that for each SerDes lane, write BnTTLCRy0 = + * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000. + + */ +static void check_erratum_a4580(uint32_t svr) +{ + const serdes_corenet_t __iomem *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + unsigned int lane; + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + if (serdes_lane_enabled(lane)) { + const struct serdes_lane __iomem *srds_lane = + &srds_regs->lane[serdes_get_lane_idx(lane)]; + + /* + * Verify that the values we were supposed to write in + * the PBI are actually there. Also, the lower 15 + * bits of res4[3] should be the same as the upper 15 + * bits of res4[1]. + */ + if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) || + (in_be32(&srds_lane->res4[1]) != 0x880000) || + (in_be32(&srds_lane->res4[3]) != 0x40000044)) { + printf("Work-around for Erratum A004580 is " + "not enabled\n"); + return; + } + } + } + + /* Everything matches, so the erratum work-around was applied */ + + printf("Work-around for Erratum A004580 enabled\n"); +} +#endif + static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 @@ -200,6 +244,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* This work-around is implemented in PBI, so just check for it */ check_erratum_a4849(svr); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004580 + /* This work-around is implemented in PBI, so just check for it */ + check_erratum_a4580(svr); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d1c1e06..1ccc5c5 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -426,6 +426,7 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #define CONFIG_SYS_FSL_ERRATUM_A004849 +#define CONFIG_SYS_FSL_ERRATUM_A004580 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 54aa71b..b61f592 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2619,7 +2619,7 @@ typedef struct serdes_corenet { #define SRDS_PCCR2_RST_XGMII1 0x00800000 #define SRDS_PCCR2_RST_XGMII2 0x00400000 u32 res5[197]; - struct { + struct serdes_lane { u32 gcr0; /* General Control Register 0 */ #define SRDS_GCR0_RRST 0x00400000 #define SRDS_GCR0_1STLANE 0x00010000 -- 2.7.4