From d5fa71e9ecc530535e48f6328490950454d086e7 Mon Sep 17 00:00:00 2001 From: Zakk Chen Date: Fri, 9 Apr 2021 06:48:29 -0700 Subject: [PATCH] [RISCV] Handle PseudoVRELOAD and PseudoVSPILL in getInstSizeInBytes. It's necessary to calculate correct instruction size because PseudoVRELOAD and PseudoSPILL will be expanded into multiple instructions. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D100702 --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 1cbfd88..8a5561a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -770,6 +770,33 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *TM.getMCAsmInfo()); } + case RISCV::PseudoVSPILL2_M1: + case RISCV::PseudoVSPILL2_M2: + case RISCV::PseudoVSPILL2_M4: + case RISCV::PseudoVSPILL3_M1: + case RISCV::PseudoVSPILL3_M2: + case RISCV::PseudoVSPILL4_M1: + case RISCV::PseudoVSPILL4_M2: + case RISCV::PseudoVSPILL5_M1: + case RISCV::PseudoVSPILL6_M1: + case RISCV::PseudoVSPILL7_M1: + case RISCV::PseudoVSPILL8_M1: + case RISCV::PseudoVRELOAD2_M1: + case RISCV::PseudoVRELOAD2_M2: + case RISCV::PseudoVRELOAD2_M4: + case RISCV::PseudoVRELOAD3_M1: + case RISCV::PseudoVRELOAD3_M2: + case RISCV::PseudoVRELOAD4_M1: + case RISCV::PseudoVRELOAD4_M2: + case RISCV::PseudoVRELOAD5_M1: + case RISCV::PseudoVRELOAD6_M1: + case RISCV::PseudoVRELOAD7_M1: + case RISCV::PseudoVRELOAD8_M1: { + // The values are determined based on expandVSPILL and expandVRELOAD that + // expand the pseudos depending on NF. + unsigned NF = isRVVSpillForZvlsseg(Opcode)->first; + return 4 * (2 * NF - 1); + } } } -- 2.7.4