From d5eb774eb6546388d9e96d7b112d9ea3d794854e Mon Sep 17 00:00:00 2001 From: Chuang-Yu Cheng Date: Mon, 28 Mar 2016 09:04:23 +0000 Subject: [PATCH] [Power9] Implement new altivec instructions: bcd* series This patch implements the following altivec instructions: - Decimal Convert From/to National/Zoned/Signed-QWord: bcdcfn. bcdcfz. bcdctn. bcdctz. bcdcfsq. bcdctsq. - Decimal Copy-Sign/Set-Sign: bcdcpsgn. bcdsetsgn. - Decimal Shift/Unsigned-Shift/Shift-and-Round: bcds. bcdus. bcdsr. - Decimal (Unsigned) Truncate: bcdtrunc. bcdutrunc. Total 13 instructions Thanks Amehsan's advice! Thanks Kit's great help! Reviewers: hal, nemanja, kbarton, tjablin, amehsan http://reviews.llvm.org/D17838 llvm-svn: 264568 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 58 ++++++++++++++++++++++ llvm/lib/Target/PowerPC/PPCInstrFormats.td | 38 ++++++++++++++ llvm/lib/Target/PowerPC/README_P9.txt | 30 +++++++++++ .../MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt | 39 +++++++++++++++ llvm/test/MC/PowerPC/ppc64-encoding-vmx.s | 47 ++++++++++++++++++ 5 files changed, 212 insertions(+) diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index a617020..e1c4673 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -1338,4 +1338,62 @@ def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$vD), (ins vrrc:$vA), // Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword def VMUL10EUQ : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>; def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>; + +// Decimal Integer Format Conversion Instructions + +// [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set. +class VX_VT5_EO5_VB5_PS1_XO9_o eo, bits<9> xo, string opc, + list pattern> + : VX_RD5_EO5_RS5_PS1_XO9 { + let Defs = [CR6]; +} + +// [PO VRT EO VRB 1 / XO] +class VX_VT5_EO5_VB5_XO9_o eo, bits<9> xo, string opc, + list pattern> + : VX_RD5_EO5_RS5_PS1_XO9 { + let Defs = [CR6]; + let PS = 0; +} + +// Decimal Convert From/to National/Zoned/Signed-QWord +def BCDCFNo : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>; +def BCDCFZo : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>; +def BCDCTNo : VX_VT5_EO5_VB5_XO9_o <5, 385, "bcdctn." , []>; +def BCDCTZo : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>; +def BCDCFSQo : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>; +def BCDCTSQo : VX_VT5_EO5_VB5_XO9_o <0, 385, "bcdctsq.", []>; + +// Decimal Copy-Sign/Set-Sign +let Defs = [CR6] in +def BCDCPSGNo : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>; + +def BCDSETSGNo : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>; + +// [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set. +class VX_VT5_VA5_VB5_PS1_XO9_o xo, string opc, list pattern> + : VX_RD5_RSp5_PS1_XO9 { + let Defs = [CR6]; +} + +// [PO VRT VRA VRB 1 / XO] +class VX_VT5_VA5_VB5_XO9_o xo, string opc, list pattern> + : VX_RD5_RSp5_PS1_XO9 { + let Defs = [CR6]; + let PS = 0; +} + +// Decimal Shift/Unsigned-Shift/Shift-and-Round +def BCDSo : VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>; +def BCDUSo : VX_VT5_VA5_VB5_XO9_o <129, "bcdus.", []>; +def BCDSRo : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>; + +// Decimal (Unsigned) Truncate +def BCDTRUNCo : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>; +def BCDUTRUNCo : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>; } // end HasP9Altivec diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td index 92780be..5f89ac5 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td @@ -1779,6 +1779,44 @@ class VXRForm_1 xo, dag OOL, dag IOL, string asmstr, let Inst{22-31} = xo; } +// VX-Form: [PO VRT EO VRB 1 PS XO] +class VX_RD5_EO5_RS5_PS1_XO9 eo, bits<9> xo, + dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list pattern> + : I<4, OOL, IOL, asmstr, itin> { + bits<5> VD; + bits<5> VB; + bit PS; + + let Pattern = pattern; + + let Inst{6-10} = VD; + let Inst{11-15} = eo; + let Inst{16-20} = VB; + let Inst{21} = 1; + let Inst{22} = PS; + let Inst{23-31} = xo; +} + +// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] +class VX_RD5_RSp5_PS1_XO9 xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list pattern> + : I<4, OOL, IOL, asmstr, itin> { + bits<5> VD; + bits<5> VA; + bits<5> VB; + bit PS; + + let Pattern = pattern; + + let Inst{6-10} = VD; + let Inst{11-15} = VA; + let Inst{16-20} = VB; + let Inst{21} = 1; + let Inst{22} = PS; + let Inst{23-31} = xo; +} + // Z23-Form (used by QPX) class Z23Form_1 opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> diff --git a/llvm/lib/Target/PowerPC/README_P9.txt b/llvm/lib/Target/PowerPC/README_P9.txt index 98e1aa5..42b4ec7 100644 --- a/llvm/lib/Target/PowerPC/README_P9.txt +++ b/llvm/lib/Target/PowerPC/README_P9.txt @@ -140,6 +140,36 @@ Altivec: VX1_Int_Ty<577, "vmul10euq", int_ppc_altivec_vmul10euq, v1i128>; VX1_Int_Ty< 65, "vmul10ecuq", int_ppc_altivec_vmul10ecuq, v1i128>; +- Decimal Convert From/to National/Zoned/Signed-QWord: + bcdcfn. bcdcfz. bcdctn. bcdctz. bcdcfsq. bcdctsq. + . Use instrinstics: + (set v1i128:$vD, (int_ppc_altivec_bcdcfno v1i128:$vB, i1:$PS)) + (set v1i128:$vD, (int_ppc_altivec_bcdcfzo v1i128:$vB, i1:$PS)) + (set v1i128:$vD, (int_ppc_altivec_bcdctno v1i128:$vB)) + (set v1i128:$vD, (int_ppc_altivec_bcdctzo v1i128:$vB, i1:$PS)) + (set v1i128:$vD, (int_ppc_altivec_bcdcfsqo v1i128:$vB, i1:$PS)) + (set v1i128:$vD, (int_ppc_altivec_bcdctsqo v1i128:$vB)) + +- Decimal Copy-Sign/Set-Sign: bcdcpsgn. bcdsetsgn. + . Use instrinstics: + (set v1i128:$vD, (int_ppc_altivec_bcdcpsgno v1i128:$vA, v1i128:$vB)) + (set v1i128:$vD, (int_ppc_altivec_bcdsetsgno v1i128:$vB, i1:$PS)) + +- Decimal Shift/Unsigned-Shift/Shift-and-Round: bcds. bcdus. bcdsr. + . Use instrinstics: + (set v1i128:$vD, (int_ppc_altivec_bcdso v1i128:$vA, v1i128:$vB, i1:$PS)) + (set v1i128:$vD, (int_ppc_altivec_bcduso v1i128:$vA, v1i128:$vB)) + (set v1i128:$vD, (int_ppc_altivec_bcdsro v1i128:$vA, v1i128:$vB, i1:$PS)) + + . Note! Their VA is accessed only 1 byte, i.e. VA.byte[7] + +- Decimal (Unsigned) Truncate: bcdtrunc. bcdutrunc. + . Use instrinstics: + (set v1i128:$vD, (int_ppc_altivec_bcdso v1i128:$vA, v1i128:$vB, i1:$PS)) + (set v1i128:$vD, (int_ppc_altivec_bcduso v1i128:$vA, v1i128:$vB)) + + . Note! Their VA is accessed only 2 byte, i.e. VA.hword[3] (VA.bit[48:63]) + VSX: - QP Copy Sign: xscpsgnqp . Similar to xscpsgndp diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt index 7fb37d6..b2b4976 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt @@ -837,3 +837,42 @@ # CHECK: vmul10ecuq 2, 3, 4 0x10 0x43 0x20 0x41 + +# CHECK: bcdcfn. 27, 31, 1 +0x13 0x67 0xff 0x81 + +# CHECK: bcdcfz. 27, 31, 1 +0x13 0x66 0xff 0x81 + +# CHECK: bcdctn. 27, 31 +0x13 0x65 0xfd 0x81 + +# CHECK: bcdctz. 27, 31, 1 +0x13 0x64 0xff 0x81 + +# CHECK: bcdcfsq. 27, 31, 1 +0x13 0x62 0xff 0x81 + +# CHECK: bcdctsq. 27, 31 +0x13 0x60 0xfd 0x81 + +# CHECK: bcdcpsgn. 27, 31, 7 +0x13 0x7f 0x3b 0x41 + +# CHECK: bcdsetsgn. 27, 31, 1 +0x13 0x7f 0xff 0x81 + +# CHECK: bcds. 27, 31, 7, 1 +0x13 0x7f 0x3e 0xc1 + +# CHECK: bcdus. 27, 31, 7 +0x13 0x7f 0x3c 0x81 + +# CHECK: bcdsr. 27, 31, 7, 1 +0x13 0x7f 0x3f 0xc1 + +# CHECK: bcdtrunc. 27, 31, 7, 1 +0x13 0x7f 0x3f 0x01 + +# CHECK: bcdutrunc. 27, 31, 7 +0x13 0x7f 0x3d 0x41 diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s b/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s index efa4221..7ac4ce9 100644 --- a/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s +++ b/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s @@ -932,3 +932,50 @@ # CHECK-BE: vmul10ecuq 2, 3, 4 # encoding: [0x10,0x43,0x20,0x41] # CHECK-LE: vmul10ecuq 2, 3, 4 # encoding: [0x41,0x20,0x43,0x10] vmul10ecuq 2, 3, 4 + +# Decimal Convert From/to National/Zoned/Signed-QWord +# CHECK-BE: bcdcfn. 27, 31, 1 # encoding: [0x13,0x67,0xff,0x81] +# CHECK-LE: bcdcfn. 27, 31, 1 # encoding: [0x81,0xff,0x67,0x13] + bcdcfn. 27, 31, 1 +# CHECK-BE: bcdcfz. 27, 31, 1 # encoding: [0x13,0x66,0xff,0x81] +# CHECK-LE: bcdcfz. 27, 31, 1 # encoding: [0x81,0xff,0x66,0x13] + bcdcfz. 27, 31, 1 +# CHECK-BE: bcdctn. 27, 31 # encoding: [0x13,0x65,0xfd,0x81] +# CHECK-LE: bcdctn. 27, 31 # encoding: [0x81,0xfd,0x65,0x13] + bcdctn. 27, 31 +# CHECK-BE: bcdctz. 27, 31, 1 # encoding: [0x13,0x64,0xff,0x81] +# CHECK-LE: bcdctz. 27, 31, 1 # encoding: [0x81,0xff,0x64,0x13] + bcdctz. 27, 31, 1 +# CHECK-BE: bcdcfsq. 27, 31, 1 # encoding: [0x13,0x62,0xff,0x81] +# CHECK-LE: bcdcfsq. 27, 31, 1 # encoding: [0x81,0xff,0x62,0x13] + bcdcfsq. 27, 31, 1 +# CHECK-BE: bcdctsq. 27, 31 # encoding: [0x13,0x60,0xfd,0x81] +# CHECK-LE: bcdctsq. 27, 31 # encoding: [0x81,0xfd,0x60,0x13] + bcdctsq. 27, 31 + +# Decimal Copy-Sign/Set-Sign +# CHECK-BE: bcdcpsgn. 27, 31, 7 # encoding: [0x13,0x7f,0x3b,0x41] +# CHECK-LE: bcdcpsgn. 27, 31, 7 # encoding: [0x41,0x3b,0x7f,0x13] + bcdcpsgn. 27, 31, 7 +# CHECK-BE: bcdsetsgn. 27, 31, 1 # encoding: [0x13,0x7f,0xff,0x81] +# CHECK-LE: bcdsetsgn. 27, 31, 1 # encoding: [0x81,0xff,0x7f,0x13] + bcdsetsgn. 27, 31, 1 + +# Decimal Shift/Unsigned-Shift/Shift-and-Round +# CHECK-BE: bcds. 27, 31, 7, 1 # encoding: [0x13,0x7f,0x3e,0xc1] +# CHECK-LE: bcds. 27, 31, 7, 1 # encoding: [0xc1,0x3e,0x7f,0x13] + bcds. 27, 31, 7, 1 +# CHECK-BE: bcdus. 27, 31, 7 # encoding: [0x13,0x7f,0x3c,0x81] +# CHECK-LE: bcdus. 27, 31, 7 # encoding: [0x81,0x3c,0x7f,0x13] + bcdus. 27, 31, 7 +# CHECK-BE: bcdsr. 27, 31, 7, 1 # encoding: [0x13,0x7f,0x3f,0xc1] +# CHECK-LE: bcdsr. 27, 31, 7, 1 # encoding: [0xc1,0x3f,0x7f,0x13] + bcdsr. 27, 31, 7, 1 + +# Decimal (Unsigned) Truncate +# CHECK-BE: bcdtrunc. 27, 31, 7, 1 # encoding: [0x13,0x7f,0x3f,0x01] +# CHECK-LE: bcdtrunc. 27, 31, 7, 1 # encoding: [0x01,0x3f,0x7f,0x13] + bcdtrunc. 27, 31, 7, 1 +# CHECK-BE: bcdutrunc. 27, 31, 7 # encoding: [0x13,0x7f,0x3d,0x41] +# CHECK-LE: bcdutrunc. 27, 31, 7 # encoding: [0x41,0x3d,0x7f,0x13] + bcdutrunc. 27, 31, 7 -- 2.7.4