From d5b73a70a0611fc6c082e20acb6ce056980c8323 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Mon, 22 Nov 2021 20:33:27 -0800 Subject: [PATCH] [llvm] Use range-based for loops (NFC) --- llvm/lib/CodeGen/BranchRelaxation.cpp | 4 +-- llvm/lib/CodeGen/MachineFunction.cpp | 10 ++++---- llvm/lib/Target/Hexagon/HexagonGenInsert.cpp | 14 +++------- llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp | 3 +-- llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp | 15 +++-------- llvm/lib/Target/PowerPC/PPCBranchSelector.cpp | 30 +++++++++------------- llvm/lib/Target/PowerPC/PPCCTRLoops.cpp | 12 ++++----- .../Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp | 3 +-- llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 5 ++-- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 5 ++-- llvm/lib/Target/Sparc/DelaySlotFiller.cpp | 5 ++-- llvm/lib/Target/Sparc/LeonPasses.cpp | 12 +++------ llvm/lib/Target/Sparc/SparcFrameLowering.cpp | 15 +++++------ .../Target/XCore/XCoreFrameToArgsOffsetElim.cpp | 4 +-- 14 files changed, 51 insertions(+), 86 deletions(-) diff --git a/llvm/lib/CodeGen/BranchRelaxation.cpp b/llvm/lib/CodeGen/BranchRelaxation.cpp index 50825cc..eda0f37 100644 --- a/llvm/lib/CodeGen/BranchRelaxation.cpp +++ b/llvm/lib/CodeGen/BranchRelaxation.cpp @@ -513,9 +513,7 @@ bool BranchRelaxation::relaxBranchInstructions() { // Relaxing branches involves creating new basic blocks, so re-eval // end() for termination. - for (MachineFunction::iterator I = MF->begin(); I != MF->end(); ++I) { - MachineBasicBlock &MBB = *I; - + for (MachineBasicBlock &MBB : *MF) { // Empty block? MachineBasicBlock::iterator Last = MBB.getLastNonDebugInstr(); if (Last == MBB.end()) diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index 366d068..28c645d 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -1327,9 +1327,9 @@ bool MachineJumpTableInfo::ReplaceMBBInJumpTable(unsigned Idx, assert(Old != New && "Not making a change?"); bool MadeChange = false; MachineJumpTableEntry &JTE = JumpTables[Idx]; - for (size_t j = 0, e = JTE.MBBs.size(); j != e; ++j) - if (JTE.MBBs[j] == Old) { - JTE.MBBs[j] = New; + for (MachineBasicBlock *&MBB : JTE.MBBs) + if (MBB == Old) { + MBB = New; MadeChange = true; } return MadeChange; @@ -1342,8 +1342,8 @@ void MachineJumpTableInfo::print(raw_ostream &OS) const { for (unsigned i = 0, e = JumpTables.size(); i != e; ++i) { OS << printJumpTableEntryReference(i) << ':'; - for (unsigned j = 0, f = JumpTables[i].MBBs.size(); j != f; ++j) - OS << ' ' << printMBBReference(*JumpTables[i].MBBs[j]); + for (const MachineBasicBlock *MBB : JumpTables[i].MBBs) + OS << ' ' << printMBBReference(*MBB); if (i != e) OS << '\n'; } diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp index 645b293..def8774 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp @@ -597,19 +597,13 @@ void HexagonGenInsert::dump_map() const { void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const { unsigned Index = 0; - using mf_iterator = MachineFunction::const_iterator; - - for (mf_iterator A = MFN->begin(), Z = MFN->end(); A != Z; ++A) { - const MachineBasicBlock &B = *A; + for (const MachineBasicBlock &B : *MFN) { if (!CMS->BT.reached(&B)) continue; - using mb_iterator = MachineBasicBlock::const_iterator; - - for (mb_iterator I = B.begin(), E = B.end(); I != E; ++I) { - const MachineInstr *MI = &*I; - for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) { - const MachineOperand &MO = MI->getOperand(i); + for (const MachineInstr &MI : B) { + for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) { + const MachineOperand &MO = MI.getOperand(i); if (MO.isReg() && MO.isDef()) { Register R = MO.getReg(); assert(MO.getSubReg() == 0 && "Unexpected subregister in definition"); diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 53e32b8..0fe2f74 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -1875,8 +1875,7 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop( if (TII->analyzeBranch(*ExitingBlock, TB, FB, Tmp1, false)) return nullptr; - for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) { - MachineBasicBlock *PB = *I; + for (MachineBasicBlock *PB : Preds) { bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp1, false); if (NotAnalyzed) return nullptr; diff --git a/llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp b/llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp index e404cea..f4934f0 100644 --- a/llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp @@ -56,23 +56,16 @@ bool NVPTXReplaceImageHandles::runOnMachineFunction(MachineFunction &MF) { bool Changed = false; InstrsToRemove.clear(); - for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE; - ++BI) { - for (MachineBasicBlock::iterator I = (*BI).begin(), E = (*BI).end(); - I != E; ++I) { - MachineInstr &MI = *I; + for (MachineBasicBlock &MBB : MF) + for (MachineInstr &MI : MBB) Changed |= processInstr(MI); - } - } // Now clean up any handle-access instructions // This is needed in debug mode when code cleanup passes are not executed, // but we need the handle access to be eliminated because they are not // valid instructions when image handles are disabled. - for (DenseSet::iterator I = InstrsToRemove.begin(), - E = InstrsToRemove.end(); I != E; ++I) { - (*I)->eraseFromParent(); - } + for (MachineInstr *MI : InstrsToRemove) + MI->eraseFromParent(); return Changed; } diff --git a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp index fa6713d..4cac0e3 100644 --- a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp +++ b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp @@ -120,16 +120,13 @@ unsigned PPCBSel::ComputeBlockSizes(MachineFunction &Fn) { static_cast(Fn.getSubtarget().getInstrInfo()); unsigned FuncSize = GetInitialOffset(Fn); - for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; - ++MFI) { - MachineBasicBlock *MBB = &*MFI; - + for (MachineBasicBlock &MBB : Fn) { // The end of the previous block may have extra nops if this block has an // alignment requirement. - if (MBB->getNumber() > 0) { - unsigned AlignExtra = GetAlignmentAdjustment(*MBB, FuncSize); + if (MBB.getNumber() > 0) { + unsigned AlignExtra = GetAlignmentAdjustment(MBB, FuncSize); - auto &BS = BlockSizes[MBB->getNumber()-1]; + auto &BS = BlockSizes[MBB.getNumber()-1]; BS.first += AlignExtra; BS.second = AlignExtra; @@ -138,10 +135,10 @@ unsigned PPCBSel::ComputeBlockSizes(MachineFunction &Fn) { unsigned BlockSize = 0; unsigned UnalignedBytesRemaining = 0; - for (MachineInstr &MI : *MBB) { + for (MachineInstr &MI : MBB) { unsigned MINumBytes = TII->getInstSizeInBytes(MI); if (MI.isInlineAsm() && (FirstImpreciseBlock < 0)) - FirstImpreciseBlock = MBB->getNumber(); + FirstImpreciseBlock = MBB.getNumber(); if (TII->isPrefixed(MI.getOpcode())) { NumPrefixed++; @@ -171,7 +168,7 @@ unsigned PPCBSel::ComputeBlockSizes(MachineFunction &Fn) { BlockSize += MINumBytes; } - BlockSizes[MBB->getNumber()].first = BlockSize; + BlockSizes[MBB.getNumber()].first = BlockSize; FuncSize += BlockSize; } @@ -181,16 +178,13 @@ unsigned PPCBSel::ComputeBlockSizes(MachineFunction &Fn) { /// Modify the basic block align adjustment. void PPCBSel::modifyAdjustment(MachineFunction &Fn) { unsigned Offset = GetInitialOffset(Fn); - for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; - ++MFI) { - MachineBasicBlock *MBB = &*MFI; - - if (MBB->getNumber() > 0) { - auto &BS = BlockSizes[MBB->getNumber()-1]; + for (MachineBasicBlock &MBB : Fn) { + if (MBB.getNumber() > 0) { + auto &BS = BlockSizes[MBB.getNumber()-1]; BS.first -= BS.second; Offset -= BS.second; - unsigned AlignExtra = GetAlignmentAdjustment(*MBB, Offset); + unsigned AlignExtra = GetAlignmentAdjustment(MBB, Offset); BS.first += AlignExtra; BS.second = AlignExtra; @@ -198,7 +192,7 @@ void PPCBSel::modifyAdjustment(MachineFunction &Fn) { Offset += AlignExtra; } - Offset += BlockSizes[MBB->getNumber()].first; + Offset += BlockSizes[MBB.getNumber()].first; } } diff --git a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp index b9518d6..ba48fd8 100644 --- a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp +++ b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp @@ -167,18 +167,16 @@ bool PPCCTRLoopsVerify::runOnMachineFunction(MachineFunction &MF) { // Verify that all bdnz/bdz instructions are dominated by a loop mtctr before // any other instructions that might clobber the ctr register. - for (MachineFunction::iterator I = MF.begin(), IE = MF.end(); - I != IE; ++I) { - MachineBasicBlock *MBB = &*I; - if (!MDT->isReachableFromEntry(MBB)) + for (MachineBasicBlock &MBB : MF) { + if (!MDT->isReachableFromEntry(&MBB)) continue; - for (MachineBasicBlock::iterator MII = MBB->getFirstTerminator(), - MIIE = MBB->end(); MII != MIIE; ++MII) { + for (MachineBasicBlock::iterator MII = MBB.getFirstTerminator(), + MIIE = MBB.end(); MII != MIIE; ++MII) { unsigned Opc = MII->getOpcode(); if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ || Opc == PPC::BDZ8 || Opc == PPC::BDZ) - if (!verifyCTRBranch(MBB, MII)) + if (!verifyCTRBranch(&MBB, MII)) llvm_unreachable("Invalid PPC CTR loop!"); } } diff --git a/llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp index be4c9dd..a9794dd 100644 --- a/llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp +++ b/llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp @@ -74,8 +74,7 @@ bool PPCExpandAtomicPseudo::runOnMachineFunction(MachineFunction &MF) { bool Changed = false; TII = static_cast(MF.getSubtarget().getInstrInfo()); TRI = &TII->getRegisterInfo(); - for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) { - MachineBasicBlock &MBB = *I; + for (MachineBasicBlock &MBB : MF) { for (MachineBasicBlock::iterator MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE;) { MachineInstr &MI = *MBBI; diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp index 1b08561..3ca563f 100644 --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -391,9 +391,8 @@ void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const { unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FP8Reg; - for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); - BI != BE; ++BI) - for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) { + for (MachineBasicBlock &MBB : MF) + for (MachineBasicBlock::iterator MBBI = MBB.end(); MBBI != MBB.begin();) { --MBBI; for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) { MachineOperand &MO = MBBI->getOperand(I); diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 649a150..8f789d5 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2138,9 +2138,8 @@ bool PPCInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, } static bool MBBDefinesCTR(MachineBasicBlock &MBB) { - for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end(); - I != IE; ++I) - if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8)) + for (MachineInstr &MI : MBB) + if (MI.definesRegister(PPC::CTR) || MI.definesRegister(PPC::CTR8)) return true; return false; } diff --git a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp index 7319924..eacfe85 100644 --- a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp +++ b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp @@ -53,9 +53,8 @@ namespace { // instructions to fill delay slot. F.getRegInfo().invalidateLiveness(); - for (MachineFunction::iterator FI = F.begin(), FE = F.end(); - FI != FE; ++FI) - Changed |= runOnMachineBasicBlock(*FI); + for (MachineBasicBlock &MBB : F) + Changed |= runOnMachineBasicBlock(MBB); return Changed; } diff --git a/llvm/lib/Target/Sparc/LeonPasses.cpp b/llvm/lib/Target/Sparc/LeonPasses.cpp index fa05a41..bd26710 100644 --- a/llvm/lib/Target/Sparc/LeonPasses.cpp +++ b/llvm/lib/Target/Sparc/LeonPasses.cpp @@ -42,8 +42,7 @@ bool InsertNOPLoad::runOnMachineFunction(MachineFunction &MF) { DebugLoc DL = DebugLoc(); bool Modified = false; - for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) { - MachineBasicBlock &MBB = *MFI; + for (MachineBasicBlock &MBB : MF) { for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) { MachineInstr &MI = *MBBI; unsigned Opcode = MI.getOpcode(); @@ -77,10 +76,8 @@ bool DetectRoundChange::runOnMachineFunction(MachineFunction &MF) { Subtarget = &MF.getSubtarget(); bool Modified = false; - for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) { - MachineBasicBlock &MBB = *MFI; - for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) { - MachineInstr &MI = *MBBI; + for (MachineBasicBlock &MBB : MF) { + for (MachineInstr &MI : MBB) { unsigned Opcode = MI.getOpcode(); if (Opcode == SP::CALL && MI.getNumOperands() > 0) { MachineOperand &MO = MI.getOperand(0); @@ -129,8 +126,7 @@ bool FixAllFDIVSQRT::runOnMachineFunction(MachineFunction &MF) { DebugLoc DL = DebugLoc(); bool Modified = false; - for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) { - MachineBasicBlock &MBB = *MFI; + for (MachineBasicBlock &MBB : MF) { for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) { MachineInstr &MI = *MBBI; unsigned Opcode = MI.getOpcode(); diff --git a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp index d165052..a740de9 100644 --- a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp @@ -343,19 +343,18 @@ void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const { } // Rewrite MBB's Live-ins. - for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); - MBB != E; ++MBB) { + for (MachineBasicBlock &MBB : MF) { for (unsigned reg = SP::I0_I1; reg <= SP::I6_I7; ++reg) { - if (!MBB->isLiveIn(reg)) + if (!MBB.isLiveIn(reg)) continue; - MBB->removeLiveIn(reg); - MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1); + MBB.removeLiveIn(reg); + MBB.addLiveIn(reg - SP::I0_I1 + SP::O0_O1); } for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) { - if (!MBB->isLiveIn(reg)) + if (!MBB.isLiveIn(reg)) continue; - MBB->removeLiveIn(reg); - MBB->addLiveIn(reg - SP::I0 + SP::O0); + MBB.removeLiveIn(reg); + MBB.addLiveIn(reg - SP::I0 + SP::O0); } } diff --git a/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp b/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp index b5dbdea..7183613 100644 --- a/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp +++ b/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp @@ -48,9 +48,7 @@ bool XCoreFTAOElim::runOnMachineFunction(MachineFunction &MF) { const XCoreInstrInfo &TII = *static_cast(MF.getSubtarget().getInstrInfo()); unsigned StackSize = MF.getFrameInfo().getStackSize(); - for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; - ++MFI) { - MachineBasicBlock &MBB = *MFI; + for (MachineBasicBlock &MBB : MF) { for (MachineBasicBlock::iterator MBBI = MBB.begin(), EE = MBB.end(); MBBI != EE; ++MBBI) { if (MBBI->getOpcode() == XCore::FRAME_TO_ARGS_OFFSET) { -- 2.7.4