From d55d592a921f1cd6a922bff0000f6662f8722d9c Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 19 Aug 2020 10:46:59 -0400 Subject: [PATCH] GlobalISel: Do not set observer of MachineIRBuilder in LegalizerHelper This fixes double printing of insertion debug messages in the legalizer. Try to cleanup usage of observers. Currently the use of observers is pretty hard to follow and it's not clear what is responsible for them. Observers are referenced in 3 places: 1. In the MachineFunction 2. In the MachineIRBuilder 3. In the LegalizerHelper The observers in the MachineFunction and MachineIRBuilder are both called only on insertions, and are redundant with each other. The source of the double printing was the same observer was added to both the MachineFunction, and the MachineIRBuilder. One of these references needs to be removed. Arguably observers in general should be fully removed from one or the other, but it may be useful to have a local observer in the MachineIRBuilder that is not added to the function's observers. Alternatively, the wrapper observer could manage a local observer in one place. The LegalizerHelper only ever calls the observer on changing/changed instructions, and never insertions. Logically these are two different types of observers, for changes and for insertions. Additionally, some places used the GISelObserverWrapper when they only needed a single observer they could use directly. Setting the observer in the LegalizerHelper constructor is not flexible enough if the LegalizerHelper is constructed anywhere outside the one used by the legalizer. AMDGPU calls the LegalizerHelper in RegBankSelect, and needs to use a local observer to apply the regbank to newly created instructions. Currently it accomplishes this by constructing a local MachineIRBuilder. I'm trying to move the MachineIRBuilder to be owned/maintained by the RegBankSelect pass itself, but the locally constructed LegalizerHelper would reset the observer. Mips also has a special case use of the LegalizationArtifactCombiner in applyMappingImpl; I think we do need to run the artifact combiner during RegBankSelect, but in a more consistent way outside of applyMappingImpl. --- .../GlobalISel/LegalizationArtifactCombiner.h | 4 +- .../llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 5 ++ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 9 ++-- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 60 +++++++++------------- llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 11 ++-- .../GlobalISel/legalize-ext-csedebug-output.mir | 3 -- 6 files changed, 39 insertions(+), 53 deletions(-) diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h index e42859e..e7bda3b 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h @@ -486,7 +486,7 @@ public: MachineRegisterInfo &MRI, MachineIRBuilder &Builder, SmallVectorImpl &UpdatedDefs, - GISelObserverWrapper &Observer) { + GISelChangeObserver &Observer) { if (!llvm::canReplaceReg(DstReg, SrcReg, MRI)) { Builder.buildCopy(DstReg, SrcReg); UpdatedDefs.push_back(DstReg); @@ -521,7 +521,7 @@ public: bool tryCombineUnmergeValues(MachineInstr &MI, SmallVectorImpl &DeadInsts, SmallVectorImpl &UpdatedDefs, - GISelObserverWrapper &Observer) { + GISelChangeObserver &Observer) { assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES); unsigned NumDefs = MI.getNumOperands() - 1; diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index 739600e..1ab4cd7 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -252,6 +252,11 @@ public: setDebugLoc(MI.getDebugLoc()); } + MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer) : + MachineIRBuilder(MI) { + setChangeObserver(Observer); + } + virtual ~MachineIRBuilder() = default; MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {} diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index bd0f2ec..b9e3225 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -91,17 +91,14 @@ LegalizerHelper::LegalizerHelper(MachineFunction &MF, MachineIRBuilder &Builder) : MIRBuilder(Builder), Observer(Observer), MRI(MF.getRegInfo()), LI(*MF.getSubtarget().getLegalizerInfo()), - TLI(*MF.getSubtarget().getTargetLowering()) { - MIRBuilder.setChangeObserver(Observer); -} + TLI(*MF.getSubtarget().getTargetLowering()) { } LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI, GISelChangeObserver &Observer, MachineIRBuilder &B) : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI), - TLI(*MF.getSubtarget().getTargetLowering()) { - MIRBuilder.setChangeObserver(Observer); -} + TLI(*MF.getSubtarget().getTargetLowering()) { } + LegalizerHelper::LegalizeResult LegalizerHelper::legalizeInstrStep(MachineInstr &MI) { LLVM_DEBUG(dbgs() << "Legalizing: " << MI); diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index b0578c8..17b1458 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -183,7 +183,12 @@ public: } void changingInstr(MachineInstr &MI) override {} - void changedInstr(MachineInstr &MI) override {} + void changedInstr(MachineInstr &MI) override { + // FIXME: In principle we should probably add the instruction to NewInsts, + // but the way the LegalizerHelper uses the observer, we will always see the + // registers we need to set the regbank on also referenced in a new + // instruction. + } }; } @@ -1167,10 +1172,8 @@ bool AMDGPURegisterBankInfo::applyMappingLoad(MachineInstr &MI, // 96-bit loads are only available for vector loads. We need to split this // into a 64-bit part, and 32 (unless we can widen to a 128-bit load). - MachineIRBuilder B(MI); ApplyRegBankMapping O(*this, MRI, &AMDGPU::SGPRRegBank); - GISelObserverWrapper Observer(&O); - B.setChangeObserver(Observer); + MachineIRBuilder B(MI, O); if (MMO->getAlign() < Align(16)) { LLT Part64, Part32; @@ -1209,13 +1212,10 @@ bool AMDGPURegisterBankInfo::applyMappingLoad(MachineInstr &MI, LLT PtrTy = MRI.getType(MI.getOperand(1).getReg()); MRI.setType(BasePtrReg, PtrTy); - MachineIRBuilder B(MI); - unsigned NumSplitParts = LoadTy.getSizeInBits() / MaxNonSmrdLoadSize; const LLT LoadSplitTy = LoadTy.divide(NumSplitParts); - ApplyRegBankMapping O(*this, MRI, &AMDGPU::VGPRRegBank); - GISelObserverWrapper Observer(&O); - B.setChangeObserver(Observer); + ApplyRegBankMapping Observer(*this, MRI, &AMDGPU::VGPRRegBank); + MachineIRBuilder B(MI, Observer); LegalizerHelper Helper(B.getMF(), Observer, B); if (LoadTy.isVector()) { @@ -1259,10 +1259,7 @@ bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc( const SIMachineFunctionInfo *Info = MF.getInfo(); Register SPReg = Info->getStackPtrOffsetReg(); ApplyRegBankMapping ApplyBank(*this, MRI, &AMDGPU::SGPRRegBank); - GISelObserverWrapper Observer(&ApplyBank); - - MachineIRBuilder B(MI); - B.setChangeObserver(Observer); + MachineIRBuilder B(MI, ApplyBank); auto WaveSize = B.buildConstant(LLT::scalar(32), ST.getWavefrontSizeLog2()); auto ScaledSize = B.buildShl(IntPtrTy, AllocSize, WaveSize); @@ -1552,9 +1549,7 @@ bool AMDGPURegisterBankInfo::applyMappingBFEIntrinsic( // The scalar form packs the offset and width in a single operand. ApplyRegBankMapping ApplyBank(*this, MRI, &AMDGPU::SGPRRegBank); - GISelObserverWrapper Observer(&ApplyBank); - MachineIRBuilder B(MI); - B.setChangeObserver(Observer); + MachineIRBuilder B(MI, ApplyBank); // Ensure the high bits are clear to insert the offset. auto OffsetMask = B.buildConstant(S32, maskTrailingOnes(6)); @@ -2146,9 +2141,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl( // Promote SGPR/VGPR booleans to s32 MachineFunction *MF = MI.getParent()->getParent(); ApplyRegBankMapping ApplyBank(*this, MRI, DstBank); - GISelObserverWrapper Observer(&ApplyBank); - MachineIRBuilder B(MI); - LegalizerHelper Helper(*MF, Observer, B); + MachineIRBuilder B(MI, ApplyBank); + LegalizerHelper Helper(*MF, ApplyBank, B); if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized) llvm_unreachable("widen scalar should have succeeded"); @@ -2291,9 +2285,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl( MachineFunction *MF = MI.getParent()->getParent(); ApplyRegBankMapping ApplyBank(*this, MRI, DstBank); - GISelObserverWrapper Observer(&ApplyBank); - MachineIRBuilder B(MI); - LegalizerHelper Helper(*MF, Observer, B); + MachineIRBuilder B(MI, ApplyBank); + LegalizerHelper Helper(*MF, ApplyBank, B); if (Helper.widenScalar(MI, 0, LLT::scalar(32)) != LegalizerHelper::Legalized) @@ -2365,13 +2358,10 @@ void AMDGPURegisterBankInfo::applyMappingImpl( const LLT S32 = LLT::scalar(32); MachineBasicBlock *MBB = MI.getParent(); MachineFunction *MF = MBB->getParent(); - MachineIRBuilder B(MI); ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank); - GISelObserverWrapper Observer(&ApplySALU); + MachineIRBuilder B(MI, ApplySALU); if (DstTy.isVector()) { - B.setChangeObserver(Observer); - Register WideSrc0Lo, WideSrc0Hi; Register WideSrc1Lo, WideSrc1Hi; @@ -2384,7 +2374,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl( B.buildBuildVectorTrunc(DstReg, {Lo.getReg(0), Hi.getReg(0)}); MI.eraseFromParent(); } else { - LegalizerHelper Helper(*MF, Observer, B); + LegalizerHelper Helper(*MF, ApplySALU, B); if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized) llvm_unreachable("widen scalar should have succeeded"); @@ -2421,8 +2411,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl( if (Ty == V2S16) { ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank); - GISelObserverWrapper Observer(&ApplySALU); - B.setChangeObserver(Observer); + B.setChangeObserver(ApplySALU); // Need to widen to s32, and expand as cmp + select, and avoid producing // illegal vector extends or unmerges that would need further @@ -2454,8 +2443,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl( MI.eraseFromParent(); } else if (Ty == S16) { ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank); - GISelObserverWrapper Observer(&ApplySALU); - LegalizerHelper Helper(*MF, Observer, B); + B.setChangeObserver(ApplySALU); + LegalizerHelper Helper(*MF, ApplySALU, B); // Need to widen to s32, and expand as cmp + select. if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized) @@ -2509,9 +2498,6 @@ void AMDGPURegisterBankInfo::applyMappingImpl( case AMDGPU::G_CTPOP: case AMDGPU::G_CTLZ_ZERO_UNDEF: case AMDGPU::G_CTTZ_ZERO_UNDEF: { - MachineIRBuilder B(MI); - MachineFunction &MF = B.getMF(); - const RegisterBank *DstBank = OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; if (DstBank == &AMDGPU::SGPRRegBank) @@ -2524,8 +2510,10 @@ void AMDGPURegisterBankInfo::applyMappingImpl( break; ApplyRegBankMapping ApplyVALU(*this, MRI, &AMDGPU::VGPRRegBank); - GISelObserverWrapper Observer(&ApplyVALU); - LegalizerHelper Helper(MF, Observer, B); + MachineIRBuilder B(MI, ApplyVALU); + + MachineFunction &MF = B.getMF(); + LegalizerHelper Helper(MF, ApplyVALU, B); if (Helper.narrowScalar(MI, 1, S32) != LegalizerHelper::Legalized) llvm_unreachable("narrowScalar should have succeeded"); diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp index d56a926..3101820 100644 --- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -716,7 +716,7 @@ void MipsRegisterBankInfo::setRegBank(MachineInstr &MI, static void combineAwayG_UNMERGE_VALUES(LegalizationArtifactCombiner &ArtCombiner, - MachineInstr &MI, GISelObserverWrapper &Observer) { + MachineInstr &MI, GISelChangeObserver &Observer) { SmallVector UpdatedDefs; SmallVector DeadInstrs; ArtCombiner.tryCombineUnmergeValues(MI, DeadInstrs, UpdatedDefs, Observer); @@ -728,14 +728,13 @@ void MipsRegisterBankInfo::applyMappingImpl( const OperandsMapper &OpdMapper) const { MachineInstr &MI = OpdMapper.getMI(); InstListTy NewInstrs; - MachineIRBuilder B(MI); MachineFunction *MF = MI.getMF(); MachineRegisterInfo &MRI = OpdMapper.getMRI(); const LegalizerInfo &LegInfo = *MF->getSubtarget().getLegalizerInfo(); InstManager NewInstrObserver(NewInstrs); - GISelObserverWrapper WrapperObserver(&NewInstrObserver); - LegalizerHelper Helper(*MF, WrapperObserver, B); + MachineIRBuilder B(MI, NewInstrObserver); + LegalizerHelper Helper(*MF, NewInstrObserver, B); LegalizationArtifactCombiner ArtCombiner(B, MF->getRegInfo(), LegInfo); switch (MI.getOpcode()) { @@ -752,7 +751,7 @@ void MipsRegisterBankInfo::applyMappingImpl( // not be considered for regbank selection. RegBankSelect for mips // visits/makes corresponding G_MERGE first. Combine them here. if (NewMI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES) - combineAwayG_UNMERGE_VALUES(ArtCombiner, *NewMI, WrapperObserver); + combineAwayG_UNMERGE_VALUES(ArtCombiner, *NewMI, NewInstrObserver); // This G_MERGE will be combined away when its corresponding G_UNMERGE // gets regBankSelected. else if (NewMI->getOpcode() == TargetOpcode::G_MERGE_VALUES) @@ -764,7 +763,7 @@ void MipsRegisterBankInfo::applyMappingImpl( return; } case TargetOpcode::G_UNMERGE_VALUES: - combineAwayG_UNMERGE_VALUES(ArtCombiner, MI, WrapperObserver); + combineAwayG_UNMERGE_VALUES(ArtCombiner, MI, NewInstrObserver); return; default: break; diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir index 00db342..3fbe904 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir @@ -11,11 +11,8 @@ body: | ; CHECK: CSEInfo::Add MI: %{{[0-9]+}}:_(s8) = G_TRUNC ; CHECK: CSEInfo::Add MI: %{{[0-9]+}}:_(s32) = G_ZEXT ; CHECK: CSEInfo::Recording new MI G_CONSTANT - ; CHECK: CSEInfo::Recording new MI G_CONSTANT - ; CHECK: CSEInfo::Recording new MI G_TRUNC ; CHECK: CSEInfo::Recording new MI G_TRUNC ; CHECK: CSEInfo::Recording new MI G_AND - ; CHECK: CSEInfo::Recording new MI G_AND ; CHECK: CSEInfo::Found Instr %{{[0-9]+}}:_(s32) = G_CONSTANT ; CHECK: CSEInfo::Found Instr %{{[0-9]+}}:_(s32) = G_TRUNC ; CHECK: CSEInfo::Found Instr %{{[0-9]+}}:_(s32) = G_AND -- 2.7.4