From d5570a72439b2d972c915208266440c2f330d03d Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Fri, 7 Sep 2012 19:43:41 -0700 Subject: [PATCH] drm/i915: POSTING_READ the new rps value In order to keep our cached values in sync with the hardware, we need a posting read here. CC: Chris Wilson Signed-off-by: Ben Widawsky Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 36c6409..4e86037 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2338,6 +2338,8 @@ void gen6_set_rps(struct drm_device *dev, u8 val) */ I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); + POSTING_READ(GEN6_RPNSWREQ); + dev_priv->rps.cur_delay = val; trace_intel_gpu_freq_change(val * 50); -- 2.7.4