From d532da6e964e60811cbc03998cd4e2ee5f6991f5 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 25 Feb 2022 08:44:07 +0100 Subject: [PATCH] radv: fix the CS regalloc hang workaround on GFX6 and few GFX7 chips RadeonSI uses a different terminology and info->blocks is actually the number of threads, not the number of blocks (ie. info->grid). Found by inspection. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index c1795b5..8acfaf2 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -7378,8 +7378,10 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_inf { bool has_prefetch = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7; bool pipeline_is_dirty = pipeline != cmd_buffer->state.emitted_compute_pipeline; + struct radv_shader *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE]; + unsigned *cs_block_size = compute_shader->info.cs.block_size; bool cs_regalloc_hang = cmd_buffer->device->physical_device->rad_info.has_cs_regalloc_hang_bug && - info->blocks[0] * info->blocks[1] * info->blocks[2] > 256; + cs_block_size[0] * cs_block_size[1] * cs_block_size[2] > 256; if (cs_regalloc_hang) cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH | -- 2.7.4