From d4362225e8cbd4416ab08f3b4b98622b70817d6a Mon Sep 17 00:00:00 2001 From: Ping Gao Date: Fri, 28 Oct 2016 10:21:45 +0800 Subject: [PATCH] drm/i915/gvt: update misc ctl regs base on stepping info Misc ctl related registers are for WA purpose, should detect the stepping info first before updating HW value. Signed-off-by: Ping Gao Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/handlers.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 2d97fb7..bb45d5d7 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1278,19 +1278,20 @@ static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, switch (offset) { case 0x4ddc: vgpu_vreg(vgpu, offset) = 0x8000003c; + /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */ + if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) + I915_WRITE(reg, vgpu_vreg(vgpu, offset)); break; case 0x42080: vgpu_vreg(vgpu, offset) = 0x8000; + /* WaCompressedResourceDisplayNewHashMode:skl */ + if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) + I915_WRITE(reg, vgpu_vreg(vgpu, offset)); break; default: return -EINVAL; } - /** - * TODO: need detect stepping info after gvt contain such information - * 0x4ddc enabled after C0, 0x42080 enabled after E0. - */ - I915_WRITE(reg, vgpu_vreg(vgpu, offset)); return 0; } -- 2.7.4