From d432a2db7df5d089bb022d8cbb30f6d6dc785039 Mon Sep 17 00:00:00 2001 From: Marcin Slusarz Date: Sun, 11 Nov 2012 19:52:59 +0100 Subject: [PATCH] drm/nv50: decode PGRAPH status registers on TLB flush fail SIgned-off-by: Marcin Slusarz Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/core/engine/graph/nv50.c | 76 ++++++++++++++++++++++-- 1 file changed, 72 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c index ab3b9dc..0d67e86 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c @@ -184,6 +184,65 @@ nv50_graph_tlb_flush(struct nouveau_engine *engine) return 0; } +static const struct nouveau_bitfield nv50_pgraph_status[] = { + { 0x00000001, "BUSY" }, /* set when any bit is set */ + { 0x00000002, "DISPATCH" }, + { 0x00000004, "UNK2" }, + { 0x00000008, "UNK3" }, + { 0x00000010, "UNK4" }, + { 0x00000020, "UNK5" }, + { 0x00000040, "M2MF" }, + { 0x00000080, "UNK7" }, + { 0x00000100, "CTXPROG" }, + { 0x00000200, "VFETCH" }, + { 0x00000400, "CCACHE_UNK4" }, + { 0x00000800, "STRMOUT_GSCHED_UNK5" }, + { 0x00001000, "UNK14XX" }, + { 0x00002000, "UNK24XX_CSCHED" }, + { 0x00004000, "UNK1CXX" }, + { 0x00008000, "CLIPID" }, + { 0x00010000, "ZCULL" }, + { 0x00020000, "ENG2D" }, + { 0x00040000, "UNK34XX" }, + { 0x00080000, "TPRAST" }, + { 0x00100000, "TPROP" }, + { 0x00200000, "TEX" }, + { 0x00400000, "TPVP" }, + { 0x00800000, "MP" }, + { 0x01000000, "ROP" }, + {} +}; + +static const char *const nv50_pgraph_vstatus_0[] = { + "VFETCH", "CCACHE", "UNK4", "UNK5", "GSCHED", "STRMOUT", "UNK14XX", NULL +}; + +static const char *const nv50_pgraph_vstatus_1[] = { + "TPRAST", "TPROP", "TEXTURE", "TPVP", "MP", NULL +}; + +static const char *const nv50_pgraph_vstatus_2[] = { + "UNK24XX", "CSCHED", "UNK1CXX", "CLIPID", "ZCULL", "ENG2D", "UNK34XX", + "ROP", NULL +}; + +static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r, + const char *const units[], u32 status) +{ + int i; + + nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status); + + for (i = 0; units[i] && status; i++) { + if ((status & 7) == 1) + pr_cont(" %s", units[i]); + status >>= 3; + } + if (status) + pr_cont(" (invalid: 0x%x)", status); + pr_cont("\n"); +} + static int nv84_graph_tlb_flush(struct nouveau_engine *engine) { @@ -219,10 +278,19 @@ nv84_graph_tlb_flush(struct nouveau_engine *engine) !(timeout = ptimer->read(ptimer) - start > 2000000000)); if (timeout) { - nv_error(priv, "PGRAPH TLB flush idle timeout fail: " - "0x%08x 0x%08x 0x%08x 0x%08x\n", - nv_rd32(priv, 0x400700), nv_rd32(priv, 0x400380), - nv_rd32(priv, 0x400384), nv_rd32(priv, 0x400388)); + nv_error(priv, "PGRAPH TLB flush idle timeout fail\n"); + + tmp = nv_rd32(priv, 0x400700); + nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp); + nouveau_bitfield_print(nv50_pgraph_status, tmp); + pr_cont("\n"); + + nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0, + nv_rd32(priv, 0x400380)); + nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1, + nv_rd32(priv, 0x400384)); + nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2, + nv_rd32(priv, 0x400388)); } nv50_vm_flush_engine(&engine->base, 0x00); -- 2.7.4