From d42925189b416b1559f3d74d663fa16c29942d96 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Wed, 5 Dec 2018 14:41:10 +0800 Subject: [PATCH] clk: mediatek: fix the PCIe MAC clock parent The PCIe function doesn't work as the clock tree of MAC layer is wrong. Hence fix the clock table. Fixes: 3b5e748615e7 ("clk: mediatek: add clock support for MT7629 SoC") Signed-off-by: Ryder Lee Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mt7629.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 200ba14..d623399 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -446,8 +446,8 @@ static const struct mtk_fixed_factor top_divs[] = { FACTOR(CLK_TOP_TO_USB3_DMA, "to_usb3_dma", "hif_sel", 1, 1), FACTOR(CLK_TOP_FROM_TOP_AHB, "from_top_ahb", "axi_sel", 1, 1), FACTOR(CLK_TOP_FROM_TOP_AXI, "from_top_axi", "hif_sel", 1, 1), - FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1), - FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1), + FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "sata_sel", 1, 1), + FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "sata_sel", 1, 1), }; static const struct mtk_gate peri_clks[] = { -- 2.7.4