From d422d3a755d25b44e66a37e487d99ca5065275a3 Mon Sep 17 00:00:00 2001 From: Clement Courbet Date: Wed, 9 Oct 2019 11:29:21 +0000 Subject: [PATCH] [llvm-exegesis][NFC] Remove extra `llvm::` qualifications. Summary: First patch: in unit tests. Subscribers: nemanjai, tschuett, MaskRay, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68687 llvm-svn: 374157 --- .../tools/llvm-exegesis/AArch64/TargetTest.cpp | 10 +- .../tools/llvm-exegesis/ARM/AssemblerTest.cpp | 16 +- .../tools/llvm-exegesis/Common/AssemblerUtils.h | 32 ++- .../tools/llvm-exegesis/PerfHelperTest.cpp | 15 +- .../tools/llvm-exegesis/PowerPC/AnalysisTest.cpp | 7 +- .../tools/llvm-exegesis/PowerPC/TargetTest.cpp | 11 +- .../tools/llvm-exegesis/RegisterValueTest.cpp | 8 +- .../tools/llvm-exegesis/X86/AssemblerTest.cpp | 4 +- .../llvm-exegesis/X86/BenchmarkResultTest.cpp | 24 +- .../llvm-exegesis/X86/RegisterAliasingTest.cpp | 39 ++- .../llvm-exegesis/X86/SchedClassResolutionTest.cpp | 2 +- .../llvm-exegesis/X86/SnippetGeneratorTest.cpp | 71 +++-- .../tools/llvm-exegesis/X86/TargetTest.cpp | 292 ++++++++++----------- 13 files changed, 250 insertions(+), 281 deletions(-) diff --git a/llvm/unittests/tools/llvm-exegesis/AArch64/TargetTest.cpp b/llvm/unittests/tools/llvm-exegesis/AArch64/TargetTest.cpp index 78c39b8..5421c17 100644 --- a/llvm/unittests/tools/llvm-exegesis/AArch64/TargetTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/AArch64/TargetTest.cpp @@ -34,10 +34,10 @@ constexpr const char kTriple[] = "aarch64-unknown-linux"; class AArch64TargetTest : public ::testing::Test { protected: AArch64TargetTest() - : ExegesisTarget_(ExegesisTarget::lookup(llvm::Triple(kTriple))) { + : ExegesisTarget_(ExegesisTarget::lookup(Triple(kTriple))) { EXPECT_THAT(ExegesisTarget_, NotNull()); std::string error; - Target_ = llvm::TargetRegistry::lookupTarget(kTriple, error); + Target_ = TargetRegistry::lookupTarget(kTriple, error); EXPECT_THAT(Target_, NotNull()); STI_.reset( Target_->createMCSubtargetInfo(kTriple, "generic", /*no features*/ "")); @@ -54,14 +54,14 @@ protected: return ExegesisTarget_->setRegTo(*STI_, Reg, Value); } - const llvm::Target *Target_; + const Target *Target_; const ExegesisTarget *const ExegesisTarget_; - std::unique_ptr STI_; + std::unique_ptr STI_; }; TEST_F(AArch64TargetTest, SetRegToConstant) { // The AArch64 target currently doesn't know how to set register values. - const auto Insts = setRegTo(llvm::AArch64::X0, llvm::APInt()); + const auto Insts = setRegTo(AArch64::X0, APInt()); EXPECT_THAT(Insts, Not(IsEmpty())); } diff --git a/llvm/unittests/tools/llvm-exegesis/ARM/AssemblerTest.cpp b/llvm/unittests/tools/llvm-exegesis/ARM/AssemblerTest.cpp index 70ad487..85fafa0 100644 --- a/llvm/unittests/tools/llvm-exegesis/ARM/AssemblerTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/ARM/AssemblerTest.cpp @@ -13,8 +13,6 @@ namespace llvm { namespace exegesis { namespace { -using llvm::MCInstBuilder; - class ARMMachineFunctionGeneratorTest : public MachineFunctionGeneratorBaseTest { protected: @@ -30,16 +28,16 @@ protected: }; TEST_F(ARMMachineFunctionGeneratorTest, DISABLED_JitFunction) { - Check({}, llvm::MCInst(), 0x1e, 0xff, 0x2f, 0xe1); + Check({}, MCInst(), 0x1e, 0xff, 0x2f, 0xe1); } TEST_F(ARMMachineFunctionGeneratorTest, DISABLED_JitFunctionADDrr) { - Check({{llvm::ARM::R0, llvm::APInt()}}, - MCInstBuilder(llvm::ARM::ADDrr) - .addReg(llvm::ARM::R0) - .addReg(llvm::ARM::R0) - .addReg(llvm::ARM::R0) - .addImm(llvm::ARMCC::AL) + Check({{ARM::R0, APInt()}}, + MCInstBuilder(ARM::ADDrr) + .addReg(ARM::R0) + .addReg(ARM::R0) + .addReg(ARM::R0) + .addImm(ARMCC::AL) .addReg(0) .addReg(0), 0x00, 0x00, 0x80, 0xe0, 0x1e, 0xff, 0x2f, 0xe1); diff --git a/llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h b/llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h index 9a348e4..795b0d6 100644 --- a/llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h +++ b/llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h @@ -31,14 +31,13 @@ protected: MachineFunctionGeneratorBaseTest(const std::string &TT, const std::string &CpuName) : TT(TT), CpuName(CpuName), - CanExecute(llvm::Triple(TT).getArch() == - llvm::Triple(llvm::sys::getProcessTriple()).getArch()), - ET(ExegesisTarget::lookup(llvm::Triple(TT))) { + CanExecute(Triple(TT).getArch() == + Triple(sys::getProcessTriple()).getArch()), + ET(ExegesisTarget::lookup(Triple(TT))) { assert(ET); if (!CanExecute) { - llvm::outs() << "Skipping execution, host:" - << llvm::sys::getProcessTriple() << ", target:" << TT - << "\n"; + outs() << "Skipping execution, host:" << sys::getProcessTriple() + << ", target:" << TT << "\n"; } } @@ -61,24 +60,23 @@ protected: } private: - std::unique_ptr createTargetMachine() { + std::unique_ptr createTargetMachine() { std::string Error; - const llvm::Target *TheTarget = - llvm::TargetRegistry::lookupTarget(TT, Error); + const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error); EXPECT_TRUE(TheTarget) << Error << " " << TT; - const llvm::TargetOptions Options; - llvm::TargetMachine *TM = TheTarget->createTargetMachine( - TT, CpuName, "", Options, llvm::Reloc::Model::Static); + const TargetOptions Options; + TargetMachine *TM = TheTarget->createTargetMachine(TT, CpuName, "", Options, + Reloc::Model::Static); EXPECT_TRUE(TM) << TT << " " << CpuName; - return std::unique_ptr( - static_cast(TM)); + return std::unique_ptr( + static_cast(TM)); } ExecutableFunction - assembleToFunction(llvm::ArrayRef RegisterInitialValues, + assembleToFunction(ArrayRef RegisterInitialValues, FillFunction Fill) { - llvm::SmallString<256> Buffer; - llvm::raw_svector_ostream AsmStream(Buffer); + SmallString<256> Buffer; + raw_svector_ostream AsmStream(Buffer); assembleToStream(*ET, createTargetMachine(), /*LiveIns=*/{}, RegisterInitialValues, Fill, AsmStream); return ExecutableFunction(createTargetMachine(), diff --git a/llvm/unittests/tools/llvm-exegesis/PerfHelperTest.cpp b/llvm/unittests/tools/llvm-exegesis/PerfHelperTest.cpp index 39942af..7ff256f 100644 --- a/llvm/unittests/tools/llvm-exegesis/PerfHelperTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/PerfHelperTest.cpp @@ -27,13 +27,14 @@ TEST(PerfHelperTest, FunctionalTest) { std::string CallbackEventName; std::string CallbackEventNameFullyQualifed; int64_t CallbackEventCycles; - Measure(llvm::makeArrayRef(SingleEvent), - [&](const PerfEvent &Event, int64_t Value) { - CallbackEventName = Event.name(); - CallbackEventNameFullyQualifed = Event.getPfmEventString(); - CallbackEventCycles = Value; - }, - EmptyFn); + Measure( + makeArrayRef(SingleEvent), + [&](const PerfEvent &Event, int64_t Value) { + CallbackEventName = Event.name(); + CallbackEventNameFullyQualifed = Event.getPfmEventString(); + CallbackEventCycles = Value; + }, + EmptyFn); EXPECT_EQ(CallbackEventName, "CYCLES:u"); EXPECT_THAT(CallbackEventNameFullyQualifed, Not(IsEmpty())); pfmTerminate(); diff --git a/llvm/unittests/tools/llvm-exegesis/PowerPC/AnalysisTest.cpp b/llvm/unittests/tools/llvm-exegesis/PowerPC/AnalysisTest.cpp index a7d2c6d..cce37d1 100644 --- a/llvm/unittests/tools/llvm-exegesis/PowerPC/AnalysisTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/PowerPC/AnalysisTest.cpp @@ -28,10 +28,9 @@ protected: AnalysisTest() { const std::string TT = "powerpc64le-unknown-linux"; std::string error; - const llvm::Target *const TheTarget = - llvm::TargetRegistry::lookupTarget(TT, error); + const Target *const TheTarget = TargetRegistry::lookupTarget(TT, error); if (!TheTarget) { - llvm::errs() << error << "\n"; + errs() << error << "\n"; return; } STI.reset(TheTarget->createMCSubtargetInfo(TT, "pwr9", "")); @@ -63,7 +62,7 @@ protected: } protected: - std::unique_ptr STI; + std::unique_ptr STI; uint16_t ALUIdx = 0; uint16_t ALUEIdx = 0; uint16_t ALUOIdx = 0; diff --git a/llvm/unittests/tools/llvm-exegesis/PowerPC/TargetTest.cpp b/llvm/unittests/tools/llvm-exegesis/PowerPC/TargetTest.cpp index 3f6c5b6..a1b628f 100644 --- a/llvm/unittests/tools/llvm-exegesis/PowerPC/TargetTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/PowerPC/TargetTest.cpp @@ -33,10 +33,10 @@ constexpr const char kTriple[] = "powerpc64le-unknown-linux"; class PowerPCTargetTest : public ::testing::Test { protected: PowerPCTargetTest() - : ExegesisTarget_(ExegesisTarget::lookup(llvm::Triple(kTriple))) { + : ExegesisTarget_(ExegesisTarget::lookup(Triple(kTriple))) { EXPECT_THAT(ExegesisTarget_, NotNull()); std::string error; - Target_ = llvm::TargetRegistry::lookupTarget(kTriple, error); + Target_ = TargetRegistry::lookupTarget(kTriple, error); EXPECT_THAT(Target_, NotNull()); } static void SetUpTestCase() { @@ -46,15 +46,14 @@ protected: InitializePowerPCExegesisTarget(); } - const llvm::Target *Target_; + const Target *Target_; const ExegesisTarget *const ExegesisTarget_; }; TEST_F(PowerPCTargetTest, SetRegToConstant) { - const std::unique_ptr STI( + const std::unique_ptr STI( Target_->createMCSubtargetInfo(kTriple, "generic", "")); - const auto Insts = - ExegesisTarget_->setRegTo(*STI, llvm::PPC::X0, llvm::APInt()); + const auto Insts = ExegesisTarget_->setRegTo(*STI, PPC::X0, APInt()); EXPECT_THAT(Insts, Not(IsEmpty())); } diff --git a/llvm/unittests/tools/llvm-exegesis/RegisterValueTest.cpp b/llvm/unittests/tools/llvm-exegesis/RegisterValueTest.cpp index a7c8ba6..21332ad 100644 --- a/llvm/unittests/tools/llvm-exegesis/RegisterValueTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/RegisterValueTest.cpp @@ -16,12 +16,12 @@ namespace exegesis { namespace { #define CHECK(EXPECTED, ACTUAL) \ - EXPECT_EQ(llvm::APInt(SizeInBits, EXPECTED, 16), \ + EXPECT_EQ(APInt(SizeInBits, EXPECTED, 16), \ bitcastFloatValue(Semantic, PredefinedValues::ACTUAL)) TEST(RegisterValueTest, Half) { const size_t SizeInBits = 16; - const auto &Semantic = llvm::APFloatBase::IEEEhalf(); + const auto &Semantic = APFloatBase::IEEEhalf(); CHECK("0000", POS_ZERO); CHECK("8000", NEG_ZERO); CHECK("3C00", ONE); @@ -37,7 +37,7 @@ TEST(RegisterValueTest, Half) { TEST(RegisterValueTest, Single) { const size_t SizeInBits = 32; - const auto &Semantic = llvm::APFloatBase::IEEEsingle(); + const auto &Semantic = APFloatBase::IEEEsingle(); CHECK("00000000", POS_ZERO); CHECK("80000000", NEG_ZERO); CHECK("3F800000", ONE); @@ -53,7 +53,7 @@ TEST(RegisterValueTest, Single) { TEST(RegisterValueTest, Double) { const size_t SizeInBits = 64; - const auto &Semantic = llvm::APFloatBase::IEEEdouble(); + const auto &Semantic = APFloatBase::IEEEdouble(); CHECK("0000000000000000", POS_ZERO); CHECK("8000000000000000", NEG_ZERO); CHECK("3FF0000000000000", ONE); diff --git a/llvm/unittests/tools/llvm-exegesis/X86/AssemblerTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/AssemblerTest.cpp index 54a33a1..a2c30e9 100644 --- a/llvm/unittests/tools/llvm-exegesis/X86/AssemblerTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/AssemblerTest.cpp @@ -38,11 +38,11 @@ protected: }; TEST_F(X86MachineFunctionGeneratorTest, DISABLED_JitFunction) { - Check({}, llvm::MCInst(), 0xc3); + Check({}, MCInst(), 0xc3); } TEST_F(X86MachineFunctionGeneratorTest, DISABLED_JitFunctionXOR32rr_X86) { - Check({{EAX, llvm::APInt(32, 1)}}, + Check({{EAX, APInt(32, 1)}}, MCInstBuilder(XOR32rr).addReg(EAX).addReg(EAX).addReg(EAX), // mov eax, 1 0xb8, 0x01, 0x00, 0x00, 0x00, diff --git a/llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp index 56cbe31..517d3ac 100644 --- a/llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp @@ -32,9 +32,9 @@ bool operator==(const BenchmarkMeasure &A, const BenchmarkMeasure &B) { std::tie(B.Key, B.PerInstructionValue, B.PerSnippetValue); } -static std::string Dump(const llvm::MCInst &McInst) { +static std::string Dump(const MCInst &McInst) { std::string Buffer; - llvm::raw_string_ostream OS(Buffer); + raw_string_ostream OS(Buffer); McInst.print(OS); return Buffer; } @@ -59,19 +59,19 @@ TEST(BenchmarkResultTest, WriteToAndReadFromDisk) { // Read benchmarks. const LLVMState State("x86_64-unknown-linux", "haswell"); - llvm::ExitOnError ExitOnErr; + ExitOnError ExitOnErr; InstructionBenchmark ToDisk; - ToDisk.Key.Instructions.push_back(llvm::MCInstBuilder(llvm::X86::XOR32rr) - .addReg(llvm::X86::AL) - .addReg(llvm::X86::AH) + ToDisk.Key.Instructions.push_back(MCInstBuilder(X86::XOR32rr) + .addReg(X86::AL) + .addReg(X86::AH) .addImm(123) .addFPImm(0.5)); ToDisk.Key.Config = "config"; ToDisk.Key.RegisterInitialValues = { - RegisterValue{llvm::X86::AL, llvm::APInt(8, "-1", 10)}, - RegisterValue{llvm::X86::AH, llvm::APInt(8, "123", 10)}}; + RegisterValue{X86::AL, APInt(8, "-1", 10)}, + RegisterValue{X86::AH, APInt(8, "123", 10)}}; ToDisk.Mode = InstructionBenchmark::Latency; ToDisk.CpuName = "cpu_name"; ToDisk.LLVMTriple = "llvm_triple"; @@ -81,12 +81,12 @@ TEST(BenchmarkResultTest, WriteToAndReadFromDisk) { ToDisk.Error = "error"; ToDisk.Info = "info"; - llvm::SmallString<64> Filename; + SmallString<64> Filename; std::error_code EC; - EC = llvm::sys::fs::createUniqueDirectory("BenchmarkResultTestDir", Filename); + EC = sys::fs::createUniqueDirectory("BenchmarkResultTestDir", Filename); ASSERT_FALSE(EC); - llvm::sys::path::append(Filename, "data.yaml"); - llvm::errs() << Filename << "-------\n"; + sys::path::append(Filename, "data.yaml"); + errs() << Filename << "-------\n"; ExitOnErr(ToDisk.writeYaml(State, Filename)); { diff --git a/llvm/unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp index 4c9dc45..a4c0bd5 100644 --- a/llvm/unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp @@ -27,16 +27,15 @@ class RegisterAliasingTest : public X86TestBase {}; TEST_F(RegisterAliasingTest, TrackSimpleRegister) { const auto &RegInfo = State.getRegInfo(); - const RegisterAliasingTracker tracker(RegInfo, llvm::X86::EAX); - std::set ActualAliasedRegisters; + const RegisterAliasingTracker tracker(RegInfo, X86::EAX); + std::set ActualAliasedRegisters; for (unsigned I : tracker.aliasedBits().set_bits()) - ActualAliasedRegisters.insert(static_cast(I)); - const std::set ExpectedAliasedRegisters = { - llvm::X86::AL, llvm::X86::AH, llvm::X86::AX, - llvm::X86::EAX, llvm::X86::HAX, llvm::X86::RAX}; + ActualAliasedRegisters.insert(static_cast(I)); + const std::set ExpectedAliasedRegisters = { + X86::AL, X86::AH, X86::AX, X86::EAX, X86::HAX, X86::RAX}; ASSERT_THAT(ActualAliasedRegisters, ExpectedAliasedRegisters); - for (llvm::MCPhysReg aliased : ExpectedAliasedRegisters) { - ASSERT_THAT(tracker.getOrigin(aliased), llvm::X86::EAX); + for (MCPhysReg aliased : ExpectedAliasedRegisters) { + ASSERT_THAT(tracker.getOrigin(aliased), X86::EAX); } } @@ -44,17 +43,16 @@ TEST_F(RegisterAliasingTest, TrackRegisterClass) { // The alias bits for GR8_ABCD_LRegClassID are the union of the alias bits for // AL, BL, CL and DL. const auto &RegInfo = State.getRegInfo(); - const llvm::BitVector NoReservedReg(RegInfo.getNumRegs()); + const BitVector NoReservedReg(RegInfo.getNumRegs()); const RegisterAliasingTracker RegClassTracker( - RegInfo, NoReservedReg, - RegInfo.getRegClass(llvm::X86::GR8_ABCD_LRegClassID)); + RegInfo, NoReservedReg, RegInfo.getRegClass(X86::GR8_ABCD_LRegClassID)); - llvm::BitVector sum(RegInfo.getNumRegs()); - sum |= RegisterAliasingTracker(RegInfo, llvm::X86::AL).aliasedBits(); - sum |= RegisterAliasingTracker(RegInfo, llvm::X86::BL).aliasedBits(); - sum |= RegisterAliasingTracker(RegInfo, llvm::X86::CL).aliasedBits(); - sum |= RegisterAliasingTracker(RegInfo, llvm::X86::DL).aliasedBits(); + BitVector sum(RegInfo.getNumRegs()); + sum |= RegisterAliasingTracker(RegInfo, X86::AL).aliasedBits(); + sum |= RegisterAliasingTracker(RegInfo, X86::BL).aliasedBits(); + sum |= RegisterAliasingTracker(RegInfo, X86::CL).aliasedBits(); + sum |= RegisterAliasingTracker(RegInfo, X86::DL).aliasedBits(); ASSERT_THAT(RegClassTracker.aliasedBits(), sum); } @@ -62,13 +60,12 @@ TEST_F(RegisterAliasingTest, TrackRegisterClass) { TEST_F(RegisterAliasingTest, TrackRegisterClassCache) { // Fetching twice the same tracker yields the same pointers. const auto &RegInfo = State.getRegInfo(); - const llvm::BitVector NoReservedReg(RegInfo.getNumRegs()); + const BitVector NoReservedReg(RegInfo.getNumRegs()); RegisterAliasingTrackerCache Cache(RegInfo, NoReservedReg); - ASSERT_THAT(&Cache.getRegister(llvm::X86::AX), - &Cache.getRegister(llvm::X86::AX)); + ASSERT_THAT(&Cache.getRegister(X86::AX), &Cache.getRegister(X86::AX)); - ASSERT_THAT(&Cache.getRegisterClass(llvm::X86::GR8_ABCD_LRegClassID), - &Cache.getRegisterClass(llvm::X86::GR8_ABCD_LRegClassID)); + ASSERT_THAT(&Cache.getRegisterClass(X86::GR8_ABCD_LRegClassID), + &Cache.getRegisterClass(X86::GR8_ABCD_LRegClassID)); } } // namespace diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SchedClassResolutionTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SchedClassResolutionTest.cpp index 7e158da..8791372 100644 --- a/llvm/unittests/tools/llvm-exegesis/X86/SchedClassResolutionTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/SchedClassResolutionTest.cpp @@ -54,7 +54,7 @@ protected: } protected: - const llvm::MCSubtargetInfo &STI; + const MCSubtargetInfo &STI; uint16_t P0Idx = 0; uint16_t P1Idx = 0; uint16_t P5Idx = 0; diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp index 9eac269..463eec2 100644 --- a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp @@ -39,7 +39,7 @@ class X86SnippetGeneratorTest : public X86TestBase { protected: X86SnippetGeneratorTest() : InstrInfo(State.getInstrInfo()) {} - const llvm::MCInstrInfo &InstrInfo; + const MCInstrInfo &InstrInfo; }; template @@ -74,11 +74,11 @@ TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) { // - Var0 [Op0] // - hasAliasingImplicitRegisters (execution is always serial) // - hasAliasingRegisters - const unsigned Opcode = llvm::X86::ADC16i16; - EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::AX); - EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[1], llvm::X86::EFLAGS); - EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[0], llvm::X86::AX); - EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[1], llvm::X86::EFLAGS); + const unsigned Opcode = X86::ADC16i16; + EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::AX); + EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[1], X86::EFLAGS); + EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[0], X86::AX); + EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[1], X86::EFLAGS); const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); ASSERT_THAT(CodeTemplates, SizeIs(1)); const auto &CT = CodeTemplates[0]; @@ -100,8 +100,8 @@ TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) { // - Var1 [Op2] // - hasTiedRegisters (execution is always serial) // - hasAliasingRegisters - const unsigned Opcode = llvm::X86::ADD16ri; - EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::EFLAGS); + const unsigned Opcode = X86::ADD16ri; + EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::EFLAGS); const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); ASSERT_THAT(CodeTemplates, SizeIs(1)); const auto &CT = CodeTemplates[0]; @@ -123,7 +123,7 @@ TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) { // - Var1 [Op1] // - Var2 [Op2] // - hasAliasingRegisters - const unsigned Opcode = llvm::X86::VXORPSrr; + const unsigned Opcode = X86::VXORPSrr; const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); ASSERT_THAT(CodeTemplates, SizeIs(1)); const auto &CT = CodeTemplates[0]; @@ -148,14 +148,14 @@ TEST_F(LatencySnippetGeneratorTest, // - Var1 [Op1] // - Var2 [Op2] // - hasAliasingRegisters - const unsigned Opcode = llvm::X86::VXORPSrr; + const unsigned Opcode = X86::VXORPSrr; randomGenerator().seed(0); // Initialize seed. const Instruction &Instr = State.getIC().getInstr(Opcode); auto AllRegisters = State.getRATC().emptyRegisters(); AllRegisters.flip(); auto Error = Generator.generateCodeTemplates(Instr, AllRegisters).takeError(); EXPECT_TRUE((bool)Error); - llvm::consumeError(std::move(Error)); + consumeError(std::move(Error)); } TEST_F(LatencySnippetGeneratorTest, DependencyThroughOtherOpcode) { @@ -165,7 +165,7 @@ TEST_F(LatencySnippetGeneratorTest, DependencyThroughOtherOpcode) { // - Op2 Implicit Def Reg(EFLAGS) // - Var0 [Op0] // - Var1 [Op1] - const unsigned Opcode = llvm::X86::CMP64rr; + const unsigned Opcode = X86::CMP64rr; const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available"; for (const auto &CT : CodeTemplates) { @@ -185,7 +185,7 @@ TEST_F(LatencySnippetGeneratorTest, LAHF) { // - LAHF // - Op0 Implicit Def Reg(AH) // - Op1 Implicit Use Reg(EFLAGS) - const unsigned Opcode = llvm::X86::LAHF; + const unsigned Opcode = X86::LAHF; const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available"; for (const auto &CT : CodeTemplates) { @@ -203,7 +203,7 @@ TEST_F(UopsSnippetGeneratorTest, ParallelInstruction) { // - Op1 Explicit Use RegClass(GR32) // - Var0 [Op0] // - Var1 [Op1] - const unsigned Opcode = llvm::X86::BNDCL32rr; + const unsigned Opcode = X86::BNDCL32rr; const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); ASSERT_THAT(CodeTemplates, SizeIs(1)); const auto &CT = CodeTemplates[0]; @@ -224,7 +224,7 @@ TEST_F(UopsSnippetGeneratorTest, SerialInstruction) { // - Op2 Implicit Use Reg(EAX) // - hasAliasingImplicitRegisters (execution is always serial) // - hasAliasingRegisters - const unsigned Opcode = llvm::X86::CDQ; + const unsigned Opcode = X86::CDQ; const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); ASSERT_THAT(CodeTemplates, SizeIs(1)); const auto &CT = CodeTemplates[0]; @@ -250,7 +250,7 @@ TEST_F(UopsSnippetGeneratorTest, StaticRenaming) { // - Var1 [Op2] // - hasTiedRegisters (execution is always serial) // - hasAliasingRegisters - const unsigned Opcode = llvm::X86::CMOV32rr; + const unsigned Opcode = X86::CMOV32rr; const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); ASSERT_THAT(CodeTemplates, SizeIs(1)); const auto &CT = CodeTemplates[0]; @@ -282,7 +282,7 @@ TEST_F(UopsSnippetGeneratorTest, NoTiedVariables) { // - Var2 [Op2] // - Var3 [Op3] // - hasAliasingRegisters - const unsigned Opcode = llvm::X86::CMOV_GR32; + const unsigned Opcode = X86::CMOV_GR32; const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); ASSERT_THAT(CodeTemplates, SizeIs(1)); const auto &CT = CodeTemplates[0]; @@ -316,7 +316,7 @@ TEST_F(UopsSnippetGeneratorTest, MemoryUse) { // - Var5 [Op5] // - hasMemoryOperands // - hasAliasingRegisters - const unsigned Opcode = llvm::X86::MOV32rm; + const unsigned Opcode = X86::MOV32rm; const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); ASSERT_THAT(CodeTemplates, SizeIs(1)); const auto &CT = CodeTemplates[0]; @@ -343,17 +343,16 @@ public: } private: - llvm::Expected> + Expected> generateCodeTemplates(const Instruction &, const BitVector &) const override { - return llvm::make_error("not implemented", - llvm::inconvertibleErrorCode()); + return make_error("not implemented", inconvertibleErrorCode()); } }; using FakeSnippetGeneratorTest = SnippetGeneratorTest; testing::Matcher IsRegisterValue(unsigned Reg, - llvm::APInt Value) { + APInt Value) { return testing::AllOf(testing::Field(&RegisterValue::Register, Reg), testing::Field(&RegisterValue::Value, Value)); } @@ -375,13 +374,13 @@ TEST_F(FakeSnippetGeneratorTest, MemoryUse_Movsb) { // - hasMemoryOperands // - hasAliasingImplicitRegisters (execution is always serial) // - hasAliasingRegisters - const unsigned Opcode = llvm::X86::MOVSB; + const unsigned Opcode = X86::MOVSB; const Instruction &Instr = State.getIC().getInstr(Opcode); auto Error = Generator.generateConfigurations(Instr, State.getRATC().emptyRegisters()) .takeError(); EXPECT_TRUE((bool)Error); - llvm::consumeError(std::move(Error)); + consumeError(std::move(Error)); } TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) { @@ -390,13 +389,12 @@ TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) { // explicit use 1 : reg RegClass=GR16 | TIED_TO:0 // explicit use 2 : imm // implicit def : EFLAGS - InstructionTemplate IT(Generator.createInstruction(llvm::X86::ADD16ri)); - IT.getValueFor(IT.Instr.Variables[0]) = - llvm::MCOperand::createReg(llvm::X86::AX); + InstructionTemplate IT(Generator.createInstruction(X86::ADD16ri)); + IT.getValueFor(IT.Instr.Variables[0]) = MCOperand::createReg(X86::AX); std::vector Snippet; Snippet.push_back(std::move(IT)); const auto RIV = Generator.computeRegisterInitialValues(Snippet); - EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(llvm::X86::AX, llvm::APInt()))); + EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::AX, APInt()))); } TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) { @@ -406,23 +404,20 @@ TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) { // -> only rbx needs defining. std::vector Snippet; { - InstructionTemplate Mov(Generator.createInstruction(llvm::X86::MOV64ri)); - Mov.getValueFor(Mov.Instr.Variables[0]) = - llvm::MCOperand::createReg(llvm::X86::RAX); - Mov.getValueFor(Mov.Instr.Variables[1]) = llvm::MCOperand::createImm(42); + InstructionTemplate Mov(Generator.createInstruction(X86::MOV64ri)); + Mov.getValueFor(Mov.Instr.Variables[0]) = MCOperand::createReg(X86::RAX); + Mov.getValueFor(Mov.Instr.Variables[1]) = MCOperand::createImm(42); Snippet.push_back(std::move(Mov)); } { - InstructionTemplate Add(Generator.createInstruction(llvm::X86::ADD64rr)); - Add.getValueFor(Add.Instr.Variables[0]) = - llvm::MCOperand::createReg(llvm::X86::RAX); - Add.getValueFor(Add.Instr.Variables[1]) = - llvm::MCOperand::createReg(llvm::X86::RBX); + InstructionTemplate Add(Generator.createInstruction(X86::ADD64rr)); + Add.getValueFor(Add.Instr.Variables[0]) = MCOperand::createReg(X86::RAX); + Add.getValueFor(Add.Instr.Variables[1]) = MCOperand::createReg(X86::RBX); Snippet.push_back(std::move(Add)); } const auto RIV = Generator.computeRegisterInitialValues(Snippet); - EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(llvm::X86::RBX, llvm::APInt()))); + EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::RBX, APInt()))); } } // namespace diff --git a/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp index d1bf120..e15b7f2 100644 --- a/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp @@ -81,26 +81,24 @@ Matcher IsMovImmediate(unsigned Opcode, int64_t Reg, int64_t Value) { Matcher IsMovValueToStack(unsigned Opcode, int64_t Value, size_t Offset) { return AllOf(OpcodeIs(Opcode), - ElementsAre(IsReg(llvm::X86::RSP), IsImm(1), IsReg(0), - IsImm(Offset), IsReg(0), IsImm(Value))); + ElementsAre(IsReg(X86::RSP), IsImm(1), IsReg(0), IsImm(Offset), + IsReg(0), IsImm(Value))); } Matcher IsMovValueFromStack(unsigned Opcode, unsigned Reg) { return AllOf(OpcodeIs(Opcode), - ElementsAre(IsReg(Reg), IsReg(llvm::X86::RSP), IsImm(1), - IsReg(0), IsImm(0), IsReg(0))); + ElementsAre(IsReg(Reg), IsReg(X86::RSP), IsImm(1), IsReg(0), + IsImm(0), IsReg(0))); } Matcher IsStackAllocate(unsigned Size) { - return AllOf( - OpcodeIs(llvm::X86::SUB64ri8), - ElementsAre(IsReg(llvm::X86::RSP), IsReg(llvm::X86::RSP), IsImm(Size))); + return AllOf(OpcodeIs(X86::SUB64ri8), + ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size))); } Matcher IsStackDeallocate(unsigned Size) { - return AllOf( - OpcodeIs(llvm::X86::ADD64ri8), - ElementsAre(IsReg(llvm::X86::RSP), IsReg(llvm::X86::RSP), IsImm(Size))); + return AllOf(OpcodeIs(X86::ADD64ri8), + ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size))); } constexpr const char kTriple[] = "x86_64-unknown-linux"; @@ -144,128 +142,121 @@ TEST_F(Core2TargetTest, NoHighByteRegs) { } TEST_F(Core2TargetTest, SetFlags) { - const unsigned Reg = llvm::X86::EFLAGS; - EXPECT_THAT( - setRegTo(Reg, APInt(64, 0x1111222233334444ULL)), - ElementsAre(IsStackAllocate(8), - IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 4), - OpcodeIs(llvm::X86::POPF64))); + const unsigned Reg = X86::EFLAGS; + EXPECT_THAT(setRegTo(Reg, APInt(64, 0x1111222233334444ULL)), + ElementsAre(IsStackAllocate(8), + IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0), + IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4), + OpcodeIs(X86::POPF64))); } TEST_F(Core2TargetTest, SetRegToGR8Value) { const uint8_t Value = 0xFFU; - const unsigned Reg = llvm::X86::AL; + const unsigned Reg = X86::AL; EXPECT_THAT(setRegTo(Reg, APInt(8, Value)), - ElementsAre(IsMovImmediate(llvm::X86::MOV8ri, Reg, Value))); + ElementsAre(IsMovImmediate(X86::MOV8ri, Reg, Value))); } TEST_F(Core2TargetTest, SetRegToGR16Value) { const uint16_t Value = 0xFFFFU; - const unsigned Reg = llvm::X86::BX; + const unsigned Reg = X86::BX; EXPECT_THAT(setRegTo(Reg, APInt(16, Value)), - ElementsAre(IsMovImmediate(llvm::X86::MOV16ri, Reg, Value))); + ElementsAre(IsMovImmediate(X86::MOV16ri, Reg, Value))); } TEST_F(Core2TargetTest, SetRegToGR32Value) { const uint32_t Value = 0x7FFFFU; - const unsigned Reg = llvm::X86::ECX; + const unsigned Reg = X86::ECX; EXPECT_THAT(setRegTo(Reg, APInt(32, Value)), - ElementsAre(IsMovImmediate(llvm::X86::MOV32ri, Reg, Value))); + ElementsAre(IsMovImmediate(X86::MOV32ri, Reg, Value))); } TEST_F(Core2TargetTest, SetRegToGR64Value) { const uint64_t Value = 0x7FFFFFFFFFFFFFFFULL; - const unsigned Reg = llvm::X86::RDX; + const unsigned Reg = X86::RDX; EXPECT_THAT(setRegTo(Reg, APInt(64, Value)), - ElementsAre(IsMovImmediate(llvm::X86::MOV64ri, Reg, Value))); + ElementsAre(IsMovImmediate(X86::MOV64ri, Reg, Value))); } TEST_F(Core2TargetTest, SetRegToVR64Value) { - EXPECT_THAT( - setRegTo(llvm::X86::MM0, APInt(64, 0x1111222233334444ULL)), - ElementsAre(IsStackAllocate(8), - IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 4), - IsMovValueFromStack(llvm::X86::MMX_MOVQ64rm, llvm::X86::MM0), - IsStackDeallocate(8))); + EXPECT_THAT(setRegTo(X86::MM0, APInt(64, 0x1111222233334444ULL)), + ElementsAre(IsStackAllocate(8), + IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0), + IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4), + IsMovValueFromStack(X86::MMX_MOVQ64rm, X86::MM0), + IsStackDeallocate(8))); } TEST_F(Core2TargetTest, SetRegToVR128Value_Use_MOVDQUrm) { EXPECT_THAT( - setRegTo(llvm::X86::XMM0, - APInt(128, "11112222333344445555666677778888", 16)), + setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)), ElementsAre(IsStackAllocate(16), - IsMovValueToStack(llvm::X86::MOV32mi, 0x77778888UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0x55556666UL, 4), - IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 8), - IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 12), - IsMovValueFromStack(llvm::X86::MOVDQUrm, llvm::X86::XMM0), + IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0), + IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4), + IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8), + IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12), + IsMovValueFromStack(X86::MOVDQUrm, X86::XMM0), IsStackDeallocate(16))); } TEST_F(Core2AvxTargetTest, SetRegToVR128Value_Use_VMOVDQUrm) { EXPECT_THAT( - setRegTo(llvm::X86::XMM0, - APInt(128, "11112222333344445555666677778888", 16)), + setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)), ElementsAre(IsStackAllocate(16), - IsMovValueToStack(llvm::X86::MOV32mi, 0x77778888UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0x55556666UL, 4), - IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 8), - IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 12), - IsMovValueFromStack(llvm::X86::VMOVDQUrm, llvm::X86::XMM0), + IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0), + IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4), + IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8), + IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12), + IsMovValueFromStack(X86::VMOVDQUrm, X86::XMM0), IsStackDeallocate(16))); } TEST_F(Core2Avx512TargetTest, SetRegToVR128Value_Use_VMOVDQU32Z128rm) { EXPECT_THAT( - setRegTo(llvm::X86::XMM0, - APInt(128, "11112222333344445555666677778888", 16)), - ElementsAre( - IsStackAllocate(16), - IsMovValueToStack(llvm::X86::MOV32mi, 0x77778888UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0x55556666UL, 4), - IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 8), - IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 12), - IsMovValueFromStack(llvm::X86::VMOVDQU32Z128rm, llvm::X86::XMM0), - IsStackDeallocate(16))); + setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)), + ElementsAre(IsStackAllocate(16), + IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0), + IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4), + IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8), + IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12), + IsMovValueFromStack(X86::VMOVDQU32Z128rm, X86::XMM0), + IsStackDeallocate(16))); } TEST_F(Core2AvxTargetTest, SetRegToVR256Value_Use_VMOVDQUYrm) { const char ValueStr[] = "1111111122222222333333334444444455555555666666667777777788888888"; - EXPECT_THAT(setRegTo(llvm::X86::YMM0, APInt(256, ValueStr, 16)), - ElementsAreArray( - {IsStackAllocate(32), - IsMovValueToStack(llvm::X86::MOV32mi, 0x88888888UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0x77777777UL, 4), - IsMovValueToStack(llvm::X86::MOV32mi, 0x66666666UL, 8), - IsMovValueToStack(llvm::X86::MOV32mi, 0x55555555UL, 12), - IsMovValueToStack(llvm::X86::MOV32mi, 0x44444444UL, 16), - IsMovValueToStack(llvm::X86::MOV32mi, 0x33333333UL, 20), - IsMovValueToStack(llvm::X86::MOV32mi, 0x22222222UL, 24), - IsMovValueToStack(llvm::X86::MOV32mi, 0x11111111UL, 28), - IsMovValueFromStack(llvm::X86::VMOVDQUYrm, llvm::X86::YMM0), - IsStackDeallocate(32)})); + EXPECT_THAT( + setRegTo(X86::YMM0, APInt(256, ValueStr, 16)), + ElementsAreArray({IsStackAllocate(32), + IsMovValueToStack(X86::MOV32mi, 0x88888888UL, 0), + IsMovValueToStack(X86::MOV32mi, 0x77777777UL, 4), + IsMovValueToStack(X86::MOV32mi, 0x66666666UL, 8), + IsMovValueToStack(X86::MOV32mi, 0x55555555UL, 12), + IsMovValueToStack(X86::MOV32mi, 0x44444444UL, 16), + IsMovValueToStack(X86::MOV32mi, 0x33333333UL, 20), + IsMovValueToStack(X86::MOV32mi, 0x22222222UL, 24), + IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 28), + IsMovValueFromStack(X86::VMOVDQUYrm, X86::YMM0), + IsStackDeallocate(32)})); } TEST_F(Core2Avx512TargetTest, SetRegToVR256Value_Use_VMOVDQU32Z256rm) { const char ValueStr[] = "1111111122222222333333334444444455555555666666667777777788888888"; EXPECT_THAT( - setRegTo(llvm::X86::YMM0, APInt(256, ValueStr, 16)), - ElementsAreArray( - {IsStackAllocate(32), - IsMovValueToStack(llvm::X86::MOV32mi, 0x88888888UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0x77777777UL, 4), - IsMovValueToStack(llvm::X86::MOV32mi, 0x66666666UL, 8), - IsMovValueToStack(llvm::X86::MOV32mi, 0x55555555UL, 12), - IsMovValueToStack(llvm::X86::MOV32mi, 0x44444444UL, 16), - IsMovValueToStack(llvm::X86::MOV32mi, 0x33333333UL, 20), - IsMovValueToStack(llvm::X86::MOV32mi, 0x22222222UL, 24), - IsMovValueToStack(llvm::X86::MOV32mi, 0x11111111UL, 28), - IsMovValueFromStack(llvm::X86::VMOVDQU32Z256rm, llvm::X86::YMM0), - IsStackDeallocate(32)})); + setRegTo(X86::YMM0, APInt(256, ValueStr, 16)), + ElementsAreArray({IsStackAllocate(32), + IsMovValueToStack(X86::MOV32mi, 0x88888888UL, 0), + IsMovValueToStack(X86::MOV32mi, 0x77777777UL, 4), + IsMovValueToStack(X86::MOV32mi, 0x66666666UL, 8), + IsMovValueToStack(X86::MOV32mi, 0x55555555UL, 12), + IsMovValueToStack(X86::MOV32mi, 0x44444444UL, 16), + IsMovValueToStack(X86::MOV32mi, 0x33333333UL, 20), + IsMovValueToStack(X86::MOV32mi, 0x22222222UL, 24), + IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 28), + IsMovValueFromStack(X86::VMOVDQU32Z256rm, X86::YMM0), + IsStackDeallocate(32)})); } TEST_F(Core2Avx512TargetTest, SetRegToVR512Value) { @@ -273,103 +264,94 @@ TEST_F(Core2Avx512TargetTest, SetRegToVR512Value) { "1111111122222222333333334444444455555555666666667777777788888888" "99999999AAAAAAAABBBBBBBBCCCCCCCCDDDDDDDDEEEEEEEEFFFFFFFF00000000"; EXPECT_THAT( - setRegTo(llvm::X86::ZMM0, APInt(512, ValueStr, 16)), - ElementsAreArray( - {IsStackAllocate(64), - IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0xFFFFFFFFUL, 4), - IsMovValueToStack(llvm::X86::MOV32mi, 0xEEEEEEEEUL, 8), - IsMovValueToStack(llvm::X86::MOV32mi, 0xDDDDDDDDUL, 12), - IsMovValueToStack(llvm::X86::MOV32mi, 0xCCCCCCCCUL, 16), - IsMovValueToStack(llvm::X86::MOV32mi, 0xBBBBBBBBUL, 20), - IsMovValueToStack(llvm::X86::MOV32mi, 0xAAAAAAAAUL, 24), - IsMovValueToStack(llvm::X86::MOV32mi, 0x99999999UL, 28), - IsMovValueToStack(llvm::X86::MOV32mi, 0x88888888UL, 32), - IsMovValueToStack(llvm::X86::MOV32mi, 0x77777777UL, 36), - IsMovValueToStack(llvm::X86::MOV32mi, 0x66666666UL, 40), - IsMovValueToStack(llvm::X86::MOV32mi, 0x55555555UL, 44), - IsMovValueToStack(llvm::X86::MOV32mi, 0x44444444UL, 48), - IsMovValueToStack(llvm::X86::MOV32mi, 0x33333333UL, 52), - IsMovValueToStack(llvm::X86::MOV32mi, 0x22222222UL, 56), - IsMovValueToStack(llvm::X86::MOV32mi, 0x11111111UL, 60), - IsMovValueFromStack(llvm::X86::VMOVDQU32Zrm, llvm::X86::ZMM0), - IsStackDeallocate(64)})); + setRegTo(X86::ZMM0, APInt(512, ValueStr, 16)), + ElementsAreArray({IsStackAllocate(64), + IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 0), + IsMovValueToStack(X86::MOV32mi, 0xFFFFFFFFUL, 4), + IsMovValueToStack(X86::MOV32mi, 0xEEEEEEEEUL, 8), + IsMovValueToStack(X86::MOV32mi, 0xDDDDDDDDUL, 12), + IsMovValueToStack(X86::MOV32mi, 0xCCCCCCCCUL, 16), + IsMovValueToStack(X86::MOV32mi, 0xBBBBBBBBUL, 20), + IsMovValueToStack(X86::MOV32mi, 0xAAAAAAAAUL, 24), + IsMovValueToStack(X86::MOV32mi, 0x99999999UL, 28), + IsMovValueToStack(X86::MOV32mi, 0x88888888UL, 32), + IsMovValueToStack(X86::MOV32mi, 0x77777777UL, 36), + IsMovValueToStack(X86::MOV32mi, 0x66666666UL, 40), + IsMovValueToStack(X86::MOV32mi, 0x55555555UL, 44), + IsMovValueToStack(X86::MOV32mi, 0x44444444UL, 48), + IsMovValueToStack(X86::MOV32mi, 0x33333333UL, 52), + IsMovValueToStack(X86::MOV32mi, 0x22222222UL, 56), + IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 60), + IsMovValueFromStack(X86::VMOVDQU32Zrm, X86::ZMM0), + IsStackDeallocate(64)})); } // Note: We always put 80 bits on the stack independently of the size of the // value. This uses a bit more space but makes the code simpler. TEST_F(Core2TargetTest, SetRegToST0_32Bits) { - EXPECT_THAT( - setRegTo(llvm::X86::ST0, APInt(32, 0x11112222ULL)), - ElementsAre(IsStackAllocate(10), - IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 4), - IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8), - OpcodeIs(llvm::X86::LD_F80m), IsStackDeallocate(10))); + EXPECT_THAT(setRegTo(X86::ST0, APInt(32, 0x11112222ULL)), + ElementsAre(IsStackAllocate(10), + IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0), + IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4), + IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8), + OpcodeIs(X86::LD_F80m), IsStackDeallocate(10))); } TEST_F(Core2TargetTest, SetRegToST1_32Bits) { - const MCInst CopySt0ToSt1 = - llvm::MCInstBuilder(llvm::X86::ST_Frr).addReg(llvm::X86::ST1); - EXPECT_THAT( - setRegTo(llvm::X86::ST1, APInt(32, 0x11112222ULL)), - ElementsAre(IsStackAllocate(10), - IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 4), - IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8), - OpcodeIs(llvm::X86::LD_F80m), CopySt0ToSt1, - IsStackDeallocate(10))); + const MCInst CopySt0ToSt1 = MCInstBuilder(X86::ST_Frr).addReg(X86::ST1); + EXPECT_THAT(setRegTo(X86::ST1, APInt(32, 0x11112222ULL)), + ElementsAre(IsStackAllocate(10), + IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0), + IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4), + IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8), + OpcodeIs(X86::LD_F80m), CopySt0ToSt1, + IsStackDeallocate(10))); } TEST_F(Core2TargetTest, SetRegToST0_64Bits) { - EXPECT_THAT( - setRegTo(llvm::X86::ST0, APInt(64, 0x1111222233334444ULL)), - ElementsAre(IsStackAllocate(10), - IsMovValueToStack(llvm::X86::MOV32mi, 0x33334444UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 4), - IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8), - OpcodeIs(llvm::X86::LD_F80m), IsStackDeallocate(10))); + EXPECT_THAT(setRegTo(X86::ST0, APInt(64, 0x1111222233334444ULL)), + ElementsAre(IsStackAllocate(10), + IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0), + IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4), + IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8), + OpcodeIs(X86::LD_F80m), IsStackDeallocate(10))); } TEST_F(Core2TargetTest, SetRegToST0_80Bits) { - EXPECT_THAT( - setRegTo(llvm::X86::ST0, APInt(80, "11112222333344445555", 16)), - ElementsAre(IsStackAllocate(10), - IsMovValueToStack(llvm::X86::MOV32mi, 0x44445555UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0x22223333UL, 4), - IsMovValueToStack(llvm::X86::MOV16mi, 0x1111UL, 8), - OpcodeIs(llvm::X86::LD_F80m), IsStackDeallocate(10))); + EXPECT_THAT(setRegTo(X86::ST0, APInt(80, "11112222333344445555", 16)), + ElementsAre(IsStackAllocate(10), + IsMovValueToStack(X86::MOV32mi, 0x44445555UL, 0), + IsMovValueToStack(X86::MOV32mi, 0x22223333UL, 4), + IsMovValueToStack(X86::MOV16mi, 0x1111UL, 8), + OpcodeIs(X86::LD_F80m), IsStackDeallocate(10))); } TEST_F(Core2TargetTest, SetRegToFP0_80Bits) { - EXPECT_THAT( - setRegTo(llvm::X86::FP0, APInt(80, "11112222333344445555", 16)), - ElementsAre(IsStackAllocate(10), - IsMovValueToStack(llvm::X86::MOV32mi, 0x44445555UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0x22223333UL, 4), - IsMovValueToStack(llvm::X86::MOV16mi, 0x1111UL, 8), - OpcodeIs(llvm::X86::LD_Fp80m), IsStackDeallocate(10))); + EXPECT_THAT(setRegTo(X86::FP0, APInt(80, "11112222333344445555", 16)), + ElementsAre(IsStackAllocate(10), + IsMovValueToStack(X86::MOV32mi, 0x44445555UL, 0), + IsMovValueToStack(X86::MOV32mi, 0x22223333UL, 4), + IsMovValueToStack(X86::MOV16mi, 0x1111UL, 8), + OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10))); } TEST_F(Core2TargetTest, SetRegToFP1_32Bits) { - EXPECT_THAT( - setRegTo(llvm::X86::FP1, APInt(32, 0x11112222ULL)), - ElementsAre(IsStackAllocate(10), - IsMovValueToStack(llvm::X86::MOV32mi, 0x11112222UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 4), - IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8), - OpcodeIs(llvm::X86::LD_Fp80m), IsStackDeallocate(10))); + EXPECT_THAT(setRegTo(X86::FP1, APInt(32, 0x11112222ULL)), + ElementsAre(IsStackAllocate(10), + IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0), + IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4), + IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8), + OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10))); } TEST_F(Core2TargetTest, SetRegToFP1_4Bits) { - EXPECT_THAT( - setRegTo(llvm::X86::FP1, APInt(4, 0x1ULL)), - ElementsAre(IsStackAllocate(10), - IsMovValueToStack(llvm::X86::MOV32mi, 0x00000001UL, 0), - IsMovValueToStack(llvm::X86::MOV32mi, 0x00000000UL, 4), - IsMovValueToStack(llvm::X86::MOV16mi, 0x0000UL, 8), - OpcodeIs(llvm::X86::LD_Fp80m), IsStackDeallocate(10))); + EXPECT_THAT(setRegTo(X86::FP1, APInt(4, 0x1ULL)), + ElementsAre(IsStackAllocate(10), + IsMovValueToStack(X86::MOV32mi, 0x00000001UL, 0), + IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4), + IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8), + OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10))); } TEST_F(Core2Avx512TargetTest, FillMemoryOperands_ADD64rm) { -- 2.7.4