From d4131814b3117c00c3eb2b0dc30b6a03297421f4 Mon Sep 17 00:00:00 2001
From: Quentin Colombet <qcolombet@apple.com>
Date: Thu, 7 Apr 2016 20:27:33 +0000
Subject: [PATCH] [GlobalISel] Add RegBankSelect hooks into the pass pipeline.
 Now, RegBankSelect will happen after the IRTranslation and the target may
 optionally add additional passes in between.

llvm-svn: 265716
---
 llvm/include/llvm/CodeGen/Passes.h               | 9 +++++++++
 llvm/lib/CodeGen/LLVMTargetMachine.cpp           | 8 ++++++++
 llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 6 ++++++
 3 files changed, 23 insertions(+)

diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h
index 61b3ea8..8275b0f 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -220,6 +220,15 @@ public:
   /// LLVM code to machine instructions with possibly generic opcodes.
   virtual bool addIRTranslator() { return true; }
 
+  /// This method may be implemented by targets that want to run passes
+  /// immediately before the register bank selection.
+  virtual void addPreRegBankSelect() {}
+
+  /// This method should install a register bank selector pass, which
+  /// assigns register banks to virtual registers without a register
+  /// class or register banks.
+  virtual bool addRegBankSelect() { return true; }
+
   /// Add the complete, standard set of LLVM CodeGen passes.
   /// Fully developed targets will not generally override this.
   virtual void addMachinePasses();
diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp
index 9c6236e..a190493 100644
--- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp
@@ -143,6 +143,14 @@ addPassesToGenerateCode(LLVMTargetMachine *TM, PassManagerBase &PM,
   if (LLVM_UNLIKELY(EnableGlobalISel)) {
     if (PassConfig->addIRTranslator())
       return nullptr;
+
+    // Before running the register bank selector, ask the target if it
+    // wants to run some passes.
+    PassConfig->addPreRegBankSelect();
+
+    if (PassConfig->addRegBankSelect())
+      return nullptr;
+
   } else if (PassConfig->addInstSelector())
     return nullptr;
 
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 9712d0e..d4de69f 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -19,6 +19,7 @@
 #ifdef LLVM_BUILD_GLOBAL_ISEL
 #  include "llvm/CodeGen/GlobalISel/IRTranslator.h"
 #endif
+#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/RegAllocRegistry.h"
 #include "llvm/IR/Function.h"
@@ -241,6 +242,7 @@ public:
   bool addInstSelector() override;
 #ifdef LLVM_BUILD_GLOBAL_ISEL
   bool addIRTranslator() override;
+  bool addRegBankSelect() override;
 #endif
   bool addILPOpts() override;
   void addPreRegAlloc() override;
@@ -339,6 +341,10 @@ bool AArch64PassConfig::addIRTranslator() {
   addPass(new IRTranslator());
   return false;
 }
+bool AArch64PassConfig::addRegBankSelect() {
+  addPass(new RegBankSelect());
+  return false;
+}
 #endif
 
 bool AArch64PassConfig::addILPOpts() {
-- 
2.7.4