From d3f2035a3c1e2684a6c91de348b0d0df443608ac Mon Sep 17 00:00:00 2001
From: Justin Holewinski <jholewinski@nvidia.com>
Date: Fri, 26 Jul 2013 13:28:29 +0000
Subject: [PATCH] Add a target legalize hook for SplitVectorOperand (again)

CustomLowerNode was not being called during SplitVectorOperand,
meaning custom legalization could not be used by targets.

This also adds a test case for NVPTX that depends on this custom
legalization.

Differential Revision: http://llvm-reviews.chandlerc.com/D1195

Attempt to fix the buildbots by making the X86 test I just added platform independent

llvm-svn: 187202
---
 .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp   |  4 +++
 llvm/lib/Target/X86/X86ISelLowering.cpp            |  2 +-
 llvm/test/CodeGen/NVPTX/vector-stores.ll           | 30 ++++++++++++++++++++++
 llvm/test/CodeGen/X86/floor-soft-float.ll          | 13 ++++++++++
 4 files changed, 48 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/NVPTX/vector-stores.ll
 create mode 100644 llvm/test/CodeGen/X86/floor-soft-float.ll

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 75bb609..72c16b5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1031,6 +1031,10 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
         dbgs() << "\n");
   SDValue Res = SDValue();
 
+  // See if the target wants to custom split this node.
+  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
+    return false;
+
   if (Res.getNode() == 0) {
     switch (N->getOpcode()) {
     default:
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e75781e..ad2d308 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -996,7 +996,7 @@ void X86TargetLowering::resetOperationActions() {
     setLoadExtAction(ISD::EXTLOAD,              MVT::v2f32, Legal);
   }
 
-  if (Subtarget->hasSSE41()) {
+  if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
     setOperationAction(ISD::FFLOOR,             MVT::f32,   Legal);
     setOperationAction(ISD::FCEIL,              MVT::f32,   Legal);
     setOperationAction(ISD::FTRUNC,             MVT::f32,   Legal);
diff --git a/llvm/test/CodeGen/NVPTX/vector-stores.ll b/llvm/test/CodeGen/NVPTX/vector-stores.ll
new file mode 100644
index 0000000..4941812
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/vector-stores.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+; CHECK: .visible .func foo1
+; CHECK: st.v2.f32
+define void @foo1(<2 x float> %val, <2 x float>* %ptr) {
+  store <2 x float> %val, <2 x float>* %ptr
+  ret void
+}
+
+; CHECK: .visible .func foo2
+; CHECK: st.v4.f32
+define void @foo2(<4 x float> %val, <4 x float>* %ptr) {
+  store <4 x float> %val, <4 x float>* %ptr
+  ret void
+}
+
+; CHECK: .visible .func foo3
+; CHECK: st.v2.u32
+define void @foo3(<2 x i32> %val, <2 x i32>* %ptr) {
+  store <2 x i32> %val, <2 x i32>* %ptr
+  ret void
+}
+
+; CHECK: .visible .func foo4
+; CHECK: st.v4.u32
+define void @foo4(<4 x i32> %val, <4 x i32>* %ptr) {
+  store <4 x i32> %val, <4 x i32>* %ptr
+  ret void
+}
+
diff --git a/llvm/test/CodeGen/X86/floor-soft-float.ll b/llvm/test/CodeGen/X86/floor-soft-float.ll
new file mode 100644
index 0000000..8e7ee09
--- /dev/null
+++ b/llvm/test/CodeGen/X86/floor-soft-float.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx -soft-float=0 | FileCheck %s --check-prefix=CHECK-HARD-FLOAT
+; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx -soft-float=1 | FileCheck %s --check-prefix=CHECK-SOFT-FLOAT
+
+target triple = "x86_64-unknown-linux-gnu"
+
+declare float @llvm.floor.f32(float)
+
+; CHECK-SOFT-FLOAT: callq floorf
+; CHECK-HARD-FLOAT: roundss $1, %xmm0, %xmm0
+define float @myfloor(float %a) {
+  %val = tail call float @llvm.floor.f32(float %a)
+  ret float %val
+}
-- 
2.7.4