From d39af942822feaccc8559b18f0ca8215c739492e Mon Sep 17 00:00:00 2001 From: Colin Xu Date: Mon, 25 Mar 2019 09:52:16 +0800 Subject: [PATCH] drm/i915/gvt: Enable synchronous flip on handling MI_DISPLAY_FLIP According to Intel GFX PRM on 01.org, the MI_DISPLAY_FLIP command can either request display plane flip synchronously or asynchronously. In synchronous flip, flip will be hold until next vsync, which is not implemented yet in GVT. In asynchronous flip, flip will happen immediately, which is current implementation. The patch enables the sync flip on handling MI_DISPLAY_FLIP, and increment flip count correctly by only increment on primary plane. v2: Use bit operation definition for flip mode. (zhenyu) Reviewed-by: Zhenyu Wang Signed-off-by: Colin Xu Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 35b4ec3..c53dbdb 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1321,8 +1321,14 @@ static int gen8_update_plane_mmio_from_mi_display_flip( info->tile_val << 10); } - vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++; - intel_vgpu_trigger_virtual_event(vgpu, info->event); + if (info->plane == PLANE_PRIMARY) + vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++; + + if (info->async_flip) + intel_vgpu_trigger_virtual_event(vgpu, info->event); + else + set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]); + return 0; } -- 2.7.4