From d32b0a92dbba0f96d5e6c930e24e8e60f3baf7b4 Mon Sep 17 00:00:00 2001 From: Nikita Shubin Date: Fri, 2 Sep 2022 10:41:03 +0300 Subject: [PATCH] docs: pmu: fix Unmatched example typo bitmap for MHPMCOUNTERx should be 0x18 and not 0x0c, we check against SBI_PMU_FIXED_CTR_MASK which assumes than first 3 bits are dedicated to mcycle, mtime and minstret, u74 has 2 hardware counters. Reported-by: Zhang Xin Signed-off-by: Nikita Shubin Reviewed-by: Anup Patel --- docs/pmu_support.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/pmu_support.md b/docs/pmu_support.md index 8751bb5..ca6ca25 100644 --- a/docs/pmu_support.md +++ b/docs/pmu_support.md @@ -93,8 +93,8 @@ pmu { */ pmu { compatible = "riscv,pmu"; - riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0xc>, - <0x0 0x1 0xffffffff 0xfff800ff 0xc>, - <0x0 0x2 0xffffffff 0xffffe0ff 0xc>; + riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>, + <0x0 0x1 0xffffffff 0xfff800ff 0x18>, + <0x0 0x2 0xffffffff 0xffffe0ff 0x18>; }; ``` -- 2.7.4