From d2c2efcebe99f4f2a3fe571f5c4560f80ef4602b Mon Sep 17 00:00:00 2001 From: "baptiste.afsa@arm.com" Date: Thu, 11 Sep 2014 08:50:48 +0000 Subject: [PATCH] ARM64: Change some incorect uses of ptrdiff_t to int64_t. R=bmeurer@chromium.org, ulan@chromium.org BUG= Review URL: https://codereview.chromium.org/559073003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23856 ce2b1a6d-e550-0410-aec6-3dcde31c8c00 --- src/arm64/assembler-arm64-inl.h | 2 +- src/arm64/assembler-arm64.cc | 10 +++++----- src/arm64/assembler-arm64.h | 14 +++++++------- src/arm64/instructions-arm64.cc | 4 ++-- src/arm64/instructions-arm64.h | 2 +- src/arm64/lithium-codegen-arm64.cc | 2 +- 6 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/arm64/assembler-arm64-inl.h b/src/arm64/assembler-arm64-inl.h index 3b24197..5e1bed1 100644 --- a/src/arm64/assembler-arm64-inl.h +++ b/src/arm64/assembler-arm64-inl.h @@ -457,7 +457,7 @@ MemOperand::MemOperand() } -MemOperand::MemOperand(Register base, ptrdiff_t offset, AddrMode addrmode) +MemOperand::MemOperand(Register base, int64_t offset, AddrMode addrmode) : base_(base), regoffset_(NoReg), offset_(offset), addrmode_(addrmode), shift_(NO_SHIFT), extend_(NO_EXTEND), shift_amount_(0) { DCHECK(base.Is64Bits() && !base.IsZero()); diff --git a/src/arm64/assembler-arm64.cc b/src/arm64/assembler-arm64.cc index 3aff8ef..c1213e9 100644 --- a/src/arm64/assembler-arm64.cc +++ b/src/arm64/assembler-arm64.cc @@ -2455,7 +2455,7 @@ void Assembler::LoadStore(const CPURegister& rt, const MemOperand& addr, LoadStoreOp op) { Instr memop = op | Rt(rt) | RnSP(addr.base()); - ptrdiff_t offset = addr.offset(); + int64_t offset = addr.offset(); if (addr.IsImmediateOffset()) { LSDataSize size = CalcLSDataSize(op); @@ -2504,18 +2504,18 @@ void Assembler::LoadStore(const CPURegister& rt, } -bool Assembler::IsImmLSUnscaled(ptrdiff_t offset) { +bool Assembler::IsImmLSUnscaled(int64_t offset) { return is_int9(offset); } -bool Assembler::IsImmLSScaled(ptrdiff_t offset, LSDataSize size) { +bool Assembler::IsImmLSScaled(int64_t offset, LSDataSize size) { bool offset_is_size_multiple = (((offset >> size) << size) == offset); return offset_is_size_multiple && is_uint12(offset >> size); } -bool Assembler::IsImmLSPair(ptrdiff_t offset, LSDataSize size) { +bool Assembler::IsImmLSPair(int64_t offset, LSDataSize size) { bool offset_is_size_multiple = (((offset >> size) << size) == offset); return offset_is_size_multiple && is_int7(offset >> size); } @@ -3103,7 +3103,7 @@ void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) { } -void PatchingAssembler::PatchAdrFar(ptrdiff_t target_offset) { +void PatchingAssembler::PatchAdrFar(int64_t target_offset) { // The code at the current instruction should be: // adr rd, 0 // nop (adr_far) diff --git a/src/arm64/assembler-arm64.h b/src/arm64/assembler-arm64.h index f01cbaf..a06c969 100644 --- a/src/arm64/assembler-arm64.h +++ b/src/arm64/assembler-arm64.h @@ -699,7 +699,7 @@ class MemOperand { public: inline MemOperand(); inline explicit MemOperand(Register base, - ptrdiff_t offset = 0, + int64_t offset = 0, AddrMode addrmode = Offset); inline explicit MemOperand(Register base, Register regoffset, @@ -715,7 +715,7 @@ class MemOperand { const Register& base() const { return base_; } const Register& regoffset() const { return regoffset_; } - ptrdiff_t offset() const { return offset_; } + int64_t offset() const { return offset_; } AddrMode addrmode() const { return addrmode_; } Shift shift() const { return shift_; } Extend extend() const { return extend_; } @@ -742,7 +742,7 @@ class MemOperand { private: Register base_; Register regoffset_; - ptrdiff_t offset_; + int64_t offset_; AddrMode addrmode_; Shift shift_; Extend extend_; @@ -1933,12 +1933,12 @@ class Assembler : public AssemblerBase { void LoadStore(const CPURegister& rt, const MemOperand& addr, LoadStoreOp op); - static bool IsImmLSUnscaled(ptrdiff_t offset); - static bool IsImmLSScaled(ptrdiff_t offset, LSDataSize size); + static bool IsImmLSUnscaled(int64_t offset); + static bool IsImmLSScaled(int64_t offset, LSDataSize size); void LoadStorePair(const CPURegister& rt, const CPURegister& rt2, const MemOperand& addr, LoadStorePairOp op); - static bool IsImmLSPair(ptrdiff_t offset, LSDataSize size); + static bool IsImmLSPair(int64_t offset, LSDataSize size); void Logical(const Register& rd, const Register& rn, @@ -2283,7 +2283,7 @@ class PatchingAssembler : public Assembler { // See definition of PatchAdrFar() for details. static const int kAdrFarPatchableNNops = 2; static const int kAdrFarPatchableNInstrs = kAdrFarPatchableNNops + 2; - void PatchAdrFar(ptrdiff_t target_offset); + void PatchAdrFar(int64_t target_offset); }; diff --git a/src/arm64/instructions-arm64.cc b/src/arm64/instructions-arm64.cc index a6ca6af..71094ba 100644 --- a/src/arm64/instructions-arm64.cc +++ b/src/arm64/instructions-arm64.cc @@ -182,8 +182,8 @@ LSDataSize CalcLSPairDataSize(LoadStorePairOp op) { } -ptrdiff_t Instruction::ImmPCOffset() { - ptrdiff_t offset; +int64_t Instruction::ImmPCOffset() { + int64_t offset; if (IsPCRelAddressing()) { // PC-relative addressing. Only ADR is supported. offset = ImmPCRel(); diff --git a/src/arm64/instructions-arm64.h b/src/arm64/instructions-arm64.h index 9f3c20f..374e246 100644 --- a/src/arm64/instructions-arm64.h +++ b/src/arm64/instructions-arm64.h @@ -338,7 +338,7 @@ class Instruction { // Find the PC offset encoded in this instruction. 'this' may be a branch or // a PC-relative addressing instruction. // The offset returned is unscaled. - ptrdiff_t ImmPCOffset(); + int64_t ImmPCOffset(); // Find the target of this instruction. 'this' may be a branch or a // PC-relative addressing instruction. diff --git a/src/arm64/lithium-codegen-arm64.cc b/src/arm64/lithium-codegen-arm64.cc index fdfec41..e584d76 100644 --- a/src/arm64/lithium-codegen-arm64.cc +++ b/src/arm64/lithium-codegen-arm64.cc @@ -1248,7 +1248,7 @@ Operand LCodeGen::ToOperand32(LOperand* op) { } -static ptrdiff_t ArgumentsOffsetWithoutFrame(ptrdiff_t index) { +static int64_t ArgumentsOffsetWithoutFrame(int index) { DCHECK(index < 0); return -(index + 1) * kPointerSize; } -- 2.7.4