From d260d97e64c0d988eab3c420ab1497037d1af26f Mon Sep 17 00:00:00 2001 From: James Hogan Date: Thu, 1 Sep 2016 17:30:10 +0100 Subject: [PATCH] MIPS: c-r4k: Drop bc_wback_inv() from icache flush The EVA conditional bc_wback_inv() at the end of flush_icache_range() to flush the modified code all the way back to RAM was apparently there for debug purposes and to accommodate the Malta EVA configuration which makes use of a physical alias, and didn't use the CP0_EBase.WG (Write Gate) bit to put the exception vector in the same physical alias where the exception vector code is written and is being flushed. Now that CP0_EBase.WG is used, lets drop this flush. Signed-off-by: James Hogan Cc: Leonid Yegoshin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14151/ Signed-off-by: Ralf Baechle --- arch/mips/mm/c-r4k.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index fa7d8d3..bbb7dfe 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -752,17 +752,6 @@ static inline void __local_r4k_flush_icache_range(unsigned long start, break; } } -#ifdef CONFIG_EVA - /* - * Due to all possible segment mappings, there might cache aliases - * caused by the bootloader being in non-EVA mode, and the CPU switching - * to EVA during early kernel init. It's best to flush the scache - * to avoid having secondary cores fetching stale data and lead to - * kernel crashes. - */ - bc_wback_inv(start, (end - start)); - __sync(); -#endif } static inline void local_r4k_flush_icache_range(unsigned long start, -- 2.7.4