From d1aabb28134a7e72ce4d6ac26b093648f5c57e88 Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Tue, 3 May 2016 00:24:32 +0000 Subject: [PATCH] livePhysRegs: Pass MBB by reference in addLive{Ins|Outs}(); NFC The block must no be nullptr for the addLiveIns()/addLiveOuts() function. llvm-svn: 268340 --- llvm/include/llvm/CodeGen/LivePhysRegs.h | 6 +++--- llvm/lib/CodeGen/ExecutionDepsFix.cpp | 2 +- llvm/lib/CodeGen/IfConversion.cpp | 12 ++++++------ llvm/lib/CodeGen/LivePhysRegs.cpp | 16 ++++++++-------- llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp | 2 +- llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp | 4 ++-- llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 4 ++-- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 2 +- llvm/lib/Target/ARM/Thumb1FrameLowering.cpp | 2 +- llvm/lib/Target/SystemZ/SystemZShortenInst.cpp | 2 +- llvm/lib/Target/X86/X86FixupBWInsts.cpp | 2 +- llvm/lib/Target/X86/X86FloatingPoint.cpp | 2 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 2 +- 13 files changed, 29 insertions(+), 29 deletions(-) diff --git a/llvm/include/llvm/CodeGen/LivePhysRegs.h b/llvm/include/llvm/CodeGen/LivePhysRegs.h index 4c1b2c7..56999f1 100644 --- a/llvm/include/llvm/CodeGen/LivePhysRegs.h +++ b/llvm/include/llvm/CodeGen/LivePhysRegs.h @@ -115,17 +115,17 @@ public: /// Adds all live-in registers of basic block @p MBB. /// Live in registers are the registers in the blocks live-in list and the /// pristine registers. - void addLiveIns(const MachineBasicBlock *MBB); + void addLiveIns(const MachineBasicBlock &MBB); /// Adds all live-out registers of basic block @p MBB. /// Live out registers are the union of the live-in registers of the successor /// blocks and pristine registers. Live out registers of the end block are the /// callee saved registers. - void addLiveOuts(const MachineBasicBlock *MBB); + void addLiveOuts(const MachineBasicBlock &MBB); /// Like addLiveOuts() but does not add pristine registers/callee saved /// registers. - void addLiveOutsNoPristines(const MachineBasicBlock *MBB); + void addLiveOutsNoPristines(const MachineBasicBlock &MBB); typedef SparseSet::const_iterator const_iterator; const_iterator begin() const { return LiveRegs.begin(); } diff --git a/llvm/lib/CodeGen/ExecutionDepsFix.cpp b/llvm/lib/CodeGen/ExecutionDepsFix.cpp index 12ea9e3..7555f40 100644 --- a/llvm/lib/CodeGen/ExecutionDepsFix.cpp +++ b/llvm/lib/CodeGen/ExecutionDepsFix.cpp @@ -560,7 +560,7 @@ void ExeDepsFix::processUndefReads(MachineBasicBlock *MBB) { LiveRegSet.init(TRI); // We do not need to care about pristine registers as they are just preserved // but not actually used in the function. - LiveRegSet.addLiveOutsNoPristines(MBB); + LiveRegSet.addLiveOutsNoPristines(*MBB); MachineInstr *UndefMI = UndefReads.back().first; unsigned OpIdx = UndefReads.back().second; diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp index ba2fa4c..8ac5a39 100644 --- a/llvm/lib/CodeGen/IfConversion.cpp +++ b/llvm/lib/CodeGen/IfConversion.cpp @@ -1136,13 +1136,13 @@ bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) { // Initialize liveins to the first BB. These are potentiall redefined by // predicated instructions. Redefs.init(TRI); - Redefs.addLiveIns(CvtBBI->BB); - Redefs.addLiveIns(NextBBI->BB); + Redefs.addLiveIns(*CvtBBI->BB); + Redefs.addLiveIns(*NextBBI->BB); // Compute a set of registers which must not be killed by instructions in // BB1: This is everything live-in to BB2. DontKill.init(TRI); - DontKill.addLiveIns(NextBBI->BB); + DontKill.addLiveIns(*NextBBI->BB); if (CvtBBI->BB->pred_size() > 1) { BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); @@ -1241,8 +1241,8 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) { // Initialize liveins to the first BB. These are potentially redefined by // predicated instructions. Redefs.init(TRI); - Redefs.addLiveIns(CvtBBI->BB); - Redefs.addLiveIns(NextBBI->BB); + Redefs.addLiveIns(*CvtBBI->BB); + Redefs.addLiveIns(*NextBBI->BB); DontKill.clear(); @@ -1396,7 +1396,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind, // Initialize liveins to the first BB. These are potentially redefined by // predicated instructions. Redefs.init(TRI); - Redefs.addLiveIns(BBI1->BB); + Redefs.addLiveIns(*BBI1->BB); // Remove the duplicated instructions at the beginnings of both paths. // Skip dbg_value instructions diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp b/llvm/lib/CodeGen/LivePhysRegs.cpp index 4945b3d..eb29550 100644 --- a/llvm/lib/CodeGen/LivePhysRegs.cpp +++ b/llvm/lib/CodeGen/LivePhysRegs.cpp @@ -143,18 +143,18 @@ static void addPristines(LivePhysRegs &LiveRegs, const MachineFunction &MF, LiveRegs.removeReg(Info.getReg()); } -void LivePhysRegs::addLiveOutsNoPristines(const MachineBasicBlock *MBB) { +void LivePhysRegs::addLiveOutsNoPristines(const MachineBasicBlock &MBB) { // To get the live-outs we simply merge the live-ins of all successors. - for (const MachineBasicBlock *Succ : MBB->successors()) + for (const MachineBasicBlock *Succ : MBB.successors()) ::addLiveIns(*this, *Succ); } -void LivePhysRegs::addLiveOuts(const MachineBasicBlock *MBB) { - const MachineFunction &MF = *MBB->getParent(); +void LivePhysRegs::addLiveOuts(const MachineBasicBlock &MBB) { + const MachineFunction &MF = *MBB.getParent(); const MachineFrameInfo &MFI = *MF.getFrameInfo(); if (MFI.isCalleeSavedInfoValid()) { addPristines(*this, MF, MFI, *TRI); - if (MBB->isReturnBlock()) { + if (MBB.isReturnBlock()) { // The return block has no successors whose live-ins we could merge // below. So instead we add the callee saved registers manually. for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) @@ -165,10 +165,10 @@ void LivePhysRegs::addLiveOuts(const MachineBasicBlock *MBB) { addLiveOutsNoPristines(MBB); } -void LivePhysRegs::addLiveIns(const MachineBasicBlock *MBB) { - const MachineFunction &MF = *MBB->getParent(); +void LivePhysRegs::addLiveIns(const MachineBasicBlock &MBB) { + const MachineFunction &MF = *MBB.getParent(); const MachineFrameInfo &MFI = *MF.getFrameInfo(); if (MFI.isCalleeSavedInfoValid()) addPristines(*this, MF, MFI, *TRI); - ::addLiveIns(*this, *MBB); + ::addLiveIns(*this, MBB); } diff --git a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp index 0d09c23..87e4eb6 100644 --- a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp +++ b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp @@ -128,7 +128,7 @@ bool StackMapLiveness::calculateLiveness(MachineFunction &MF) { DEBUG(dbgs() << "****** BB " << MBB.getName() << " ******\n"); LiveRegs.init(TRI); // FIXME: This should probably be addLiveOuts(). - LiveRegs.addLiveOutsNoPristines(&MBB); + LiveRegs.addLiveOutsNoPristines(MBB); bool HasStackMap = false; // Reverse iterate over all instructions and add the current live register // set to an instruction if we encounter a patchpoint instruction. diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp index db6dcc7..d10a9c6 100644 --- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp +++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp @@ -607,7 +607,7 @@ bool AArch64ExpandPseudo::expandCMP_SWAP( MachineOperand &New = MI.getOperand(4); LivePhysRegs LiveRegs(&TII->getRegisterInfo()); - LiveRegs.addLiveOuts(&MBB); + LiveRegs.addLiveOuts(MBB); for (auto I = std::prev(MBB.end()); I != MBBI; --I) LiveRegs.stepBackward(*I); @@ -685,7 +685,7 @@ bool AArch64ExpandPseudo::expandCMP_SWAP_128( MachineOperand &NewHi = MI.getOperand(7); LivePhysRegs LiveRegs(&TII->getRegisterInfo()); - LiveRegs.addLiveOuts(&MBB); + LiveRegs.addLiveOuts(MBB); for (auto I = std::prev(MBB.end()); I != MBBI; --I) LiveRegs.stepBackward(*I); diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 1be3724..b522067 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -775,7 +775,7 @@ bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB, MachineOperand &New = MI.getOperand(4); LivePhysRegs LiveRegs(&TII->getRegisterInfo()); - LiveRegs.addLiveOuts(&MBB); + LiveRegs.addLiveOuts(MBB); for (auto I = std::prev(MBB.end()); I != MBBI; --I) LiveRegs.stepBackward(*I); @@ -897,7 +897,7 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB, unsigned DesiredHi = TRI->getSubReg(Desired.getReg(), ARM::gsub_1); LivePhysRegs LiveRegs(&TII->getRegisterInfo()); - LiveRegs.addLiveOuts(&MBB); + LiveRegs.addLiveOuts(MBB); for (auto I = std::prev(MBB.end()); I != MBBI; --I) LiveRegs.stepBackward(*I); diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 4aad572..16a1c3c 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -566,7 +566,7 @@ void ARMLoadStoreOpt::moveLiveRegsBefore(const MachineBasicBlock &MBB, // Initialize if we never queried in this block. if (!LiveRegsValid) { LiveRegs.init(TRI); - LiveRegs.addLiveOuts(&MBB); + LiveRegs.addLiveOuts(MBB); LiveRegPos = MBB.end(); LiveRegsValid = true; } diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp index ed74d20..31828a3 100644 --- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp +++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp @@ -467,7 +467,7 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB, // Look for a temporary register to use. // First, compute the liveness information. LivePhysRegs UsedRegs(STI.getRegisterInfo()); - UsedRegs.addLiveOuts(&MBB); + UsedRegs.addLiveOuts(MBB); // The semantic of pristines changed recently and now, // the callee-saved registers that are touched in the function // are not part of the pristines set anymore. diff --git a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp index 2f31be8..08371851 100644 --- a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp +++ b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp @@ -181,7 +181,7 @@ bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) { // Set up the set of live registers at the end of MBB (live out) LiveRegs.clear(); - LiveRegs.addLiveOuts(&MBB); + LiveRegs.addLiveOuts(MBB); // Iterate backwards through the block looking for instructions to change. for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) { diff --git a/llvm/lib/Target/X86/X86FixupBWInsts.cpp b/llvm/lib/Target/X86/X86FixupBWInsts.cpp index ab562b0..7844751 100644 --- a/llvm/lib/Target/X86/X86FixupBWInsts.cpp +++ b/llvm/lib/Target/X86/X86FixupBWInsts.cpp @@ -245,7 +245,7 @@ void FixupBWInstPass::processBasicBlock(MachineFunction &MF, // to update this for each instruction. LiveRegs.clear(); // We run after PEI, so we need to AddPristinesAndCSRs. - LiveRegs.addLiveOuts(&MBB); + LiveRegs.addLiveOuts(MBB); for (auto I = MBB.rbegin(); I != MBB.rend(); ++I) { MachineInstr *NewMI = nullptr; diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp index 26c5404..9aafa896 100644 --- a/llvm/lib/Target/X86/X86FloatingPoint.cpp +++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp @@ -1624,7 +1624,7 @@ void FPS::setKillFlags(MachineBasicBlock &MBB) const { MBB.getParent()->getSubtarget().getRegisterInfo(); LivePhysRegs LPR(TRI); - LPR.addLiveOuts(&MBB); + LPR.addLiveOuts(MBB); for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend(); I != E; ++I) { diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 195f85c..035c114 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -4537,7 +4537,7 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, // as this is usually wrong to read an undef value. if (MachineBasicBlock::LQR_Unknown == LQR) { LivePhysRegs LPR(&getRegisterInfo()); - LPR.addLiveOuts(&MBB); + LPR.addLiveOuts(MBB); MachineBasicBlock::iterator I = MBB.end(); while (I != MI) { --I; -- 2.7.4