From d14080f5f477b53b146dd8c0d6bcbffa637e8a2f Mon Sep 17 00:00:00 2001 From: Jihoon Park Date: Thu, 23 Mar 2017 11:54:44 +0900 Subject: [PATCH] s5j/boot: fix chip dependent memory map s5jt200 has Internal SRAM sized in 1280KB and provides CONFIG_RAM_SIZE from configured start address. During boot stage, s5j initializes SRAM mpu setting as read/write cacheable attribution, plus SFR area to be strongly-order for strict register accessibility. s5j allows user or board dependent mpu setting for FLASH area which can be various size and start address. The FLASH sets with read/write cacheable attribution and expects proper changes corresponding to partition map. arch/arm/src/armv7-r/mpu.h has proper API set of mpu setting and keep the base address of the memory region should align to a region-sized boundary. Change-Id: I2e9c9e9070d88c8d32465fc12235bd403952445b Signed-off-by: Jihoon Park --- .../configs/sidk_s5jt200/hello_with_tash/defconfig | 1 + build/configs/sidk_s5jt200/kernel_sample/defconfig | 1 + .../configs/sidk_s5jt200/sidk_tash_wlan/defconfig | 7 +-- build/configs/sidk_s5jt200/tc/defconfig | 1 + os/arch/arm/src/s5j/Kconfig | 8 ++- os/arch/arm/src/s5j/s5j_boot.c | 70 +++++++--------------- 6 files changed, 34 insertions(+), 54 deletions(-) diff --git a/build/configs/sidk_s5jt200/hello_with_tash/defconfig b/build/configs/sidk_s5jt200/hello_with_tash/defconfig index 205c742..4d5ba17 100644 --- a/build/configs/sidk_s5jt200/hello_with_tash/defconfig +++ b/build/configs/sidk_s5jt200/hello_with_tash/defconfig @@ -206,6 +206,7 @@ CONFIG_S5J_SFLASH=y # Serial FLASH region # CONFIG_S5J_FLASH_BASE=0x04000000 +CONFIG_S5J_FLASH_MIRROR_BASE=0x60000000 CONFIG_S5J_FLASH_SIZE=0x800000 CONFIG_S5J_FLASH_SECTOR_SIZE=4096 CONFIG_S5J_BOOTLOADER_REGION_SIZE=0x400000 diff --git a/build/configs/sidk_s5jt200/kernel_sample/defconfig b/build/configs/sidk_s5jt200/kernel_sample/defconfig index bdf19b3..e09d555 100644 --- a/build/configs/sidk_s5jt200/kernel_sample/defconfig +++ b/build/configs/sidk_s5jt200/kernel_sample/defconfig @@ -206,6 +206,7 @@ CONFIG_S5J_SFLASH=y # Serial FLASH region # CONFIG_S5J_FLASH_BASE=0x04000000 +CONFIG_S5J_FLASH_MIRROR_BASE=0x60000000 CONFIG_S5J_FLASH_SIZE=0x800000 CONFIG_S5J_FLASH_SECTOR_SIZE=4096 CONFIG_S5J_BOOTLOADER_REGION_SIZE=0x400000 diff --git a/build/configs/sidk_s5jt200/sidk_tash_wlan/defconfig b/build/configs/sidk_s5jt200/sidk_tash_wlan/defconfig index b00ee4b..2f62a7a 100755 --- a/build/configs/sidk_s5jt200/sidk_tash_wlan/defconfig +++ b/build/configs/sidk_s5jt200/sidk_tash_wlan/defconfig @@ -209,6 +209,7 @@ CONFIG_S5J_SFLASH=y # Serial FLASH region # CONFIG_S5J_FLASH_BASE=0x04000000 +CONFIG_S5J_FLASH_MIRROR_BASE=0x60000000 CONFIG_S5J_FLASH_SIZE=0x800000 CONFIG_S5J_FLASH_SECTOR_SIZE=4096 CONFIG_S5J_BOOTLOADER_REGION_SIZE=0x400000 @@ -715,6 +716,7 @@ CONFIG_NET_LWIP_STATS_UDP=y CONFIG_NET_LWIP_STATS_TCP=y CONFIG_NET_LWIP_STATS_MEM=y CONFIG_NET_LWIP_STATS_SYS=y +CONFIG_NSOCKET_DESCRIPTORS=16 CONFIG_NET_SECURITY_TLS=y # CONFIG_TLS_WITH_SSS is not set CONFIG_NET_NOINTS=y @@ -741,11 +743,6 @@ CONFIG_NET_IPv4=y # Network Device Operations # # CONFIG_NETDEV_PHY_IOCTL is not set - -# -# Socket Support -# -CONFIG_NSOCKET_DESCRIPTORS=16 # CONFIG_NET_ARCH_INCR32 is not set # CONFIG_NET_ARCH_CHKSUM is not set diff --git a/build/configs/sidk_s5jt200/tc/defconfig b/build/configs/sidk_s5jt200/tc/defconfig index 7af3a62..722ec7c 100644 --- a/build/configs/sidk_s5jt200/tc/defconfig +++ b/build/configs/sidk_s5jt200/tc/defconfig @@ -206,6 +206,7 @@ CONFIG_S5J_SFLASH=y # Serial FLASH region # CONFIG_S5J_FLASH_BASE=0x04000000 +CONFIG_S5J_FLASH_MIRROR_BASE=0x60000000 CONFIG_S5J_FLASH_SIZE=0x800000 CONFIG_S5J_FLASH_SECTOR_SIZE=4096 CONFIG_S5J_BOOTLOADER_REGION_SIZE=0x400000 diff --git a/os/arch/arm/src/s5j/Kconfig b/os/arch/arm/src/s5j/Kconfig index e341778..59c26e2 100644 --- a/os/arch/arm/src/s5j/Kconfig +++ b/os/arch/arm/src/s5j/Kconfig @@ -266,7 +266,13 @@ config S5J_FLASH_BASE hex "Nor Flash start address (physical)" default 0x04000000 help - Samsung IoT uses serial nor flash memory, this needs base address of memory map + Samsung S5J SoC uses serial nor flash memory, this needs base address of memory map + +config S5J_FLASH_MIRROR_BASE + hex "Nor Flash mirrored address (physical)" + default 0x60000000 + help + Provides mirror address mapped to Nor flash with same space config S5J_FLASH_SIZE hex "Nor Flash size (KB)" diff --git a/os/arch/arm/src/s5j/s5j_boot.c b/os/arch/arm/src/s5j/s5j_boot.c index f7286ae..2f459e5 100644 --- a/os/arch/arm/src/s5j/s5j_boot.c +++ b/os/arch/arm/src/s5j/s5j_boot.c @@ -89,7 +89,6 @@ extern uint32_t _vector_start; extern uint32_t _vector_end; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -97,7 +96,7 @@ void up_copyvectorblock(void) { uint32_t *src = (uint32_t *)&_vector_start; uint32_t *end = (uint32_t *)&_vector_end; - uint32_t *dest = (uint32_t *)VECTOR_BASE; + uint32_t *dest = (uint32_t *) VECTOR_BASE; while (src < end) { *dest++ = *src++; @@ -107,68 +106,43 @@ void up_copyvectorblock(void) #ifdef CONFIG_ARMV7M_MPU int s5j_mpu_initialize(void) { - uint32_t base; - uint32_t size; - - /* flash region - * region 0 : 0x0400_0000 ++ 4MB BL1 + TinyAra OS + SSS F/W +#ifdef CONFIG_ARCH_CHIP_S5JT200 + /* + * Vector Table 0x02020000 0x02020FFF 4 + * Reserved 0x02021000 0x020217FF 2 + * BL1 0x02021800 0x020237FF 8 + * TinyARA 0x02023800 0x020E7FFF 786(WBWA) + * Reserved 0x020E8000 0x020FFFFF 96 (WBWA) + * Reserved 0x02100000 0x021FFFFF 64 (NCNB) + * WIFI 0x02110000 0x0215FFFF 320(NCNB) */ - mpu_priv_flash(0x0, 0x04000000); - /* S5JT200 memory address in below - * 0x0202_0000 ~ 0x0215_FFFF ~1280KB - * 0x0203_0000 ~ 0x0231_FFFF ~128KB - * 0x0400_0000 ~ 0x04FF_FFFF ~16MB(sidk s5jt200 has 8MB) - */ + /* Region 0, Set read only for memory area */ + mpu_priv_flash(0x0, 0x80000000); - /* access permission for available area */ /* Region 1, for ISRAM(0x0200_0000++2048KB, RW-WBWA */ mpu_user_intsram_wb(0x02000000, 0x200000); - /* Region 2,3, for wifi driver non-$(0x020E_0000++512KB(+128KB), RW-NCNB */ - mpu_priv_noncache(0x020E0000, 0x20000); + /* Region 2, wifi driver needs non-$(0x0211_0000++320KB, RW-NCNB */ mpu_priv_noncache(0x02100000, 0x80000); - /* - * Region 4 for RO in Flash : 0x0400_0000 ++ 4MB, RO-WT - * BL1 + TinyAra OS + SSS F/W, wifi F/W, CM0 F/W - */ - base = CONFIG_S5J_FLASH_BASE; - size = CONFIG_S5J_BOOTLOADER_REGION_SIZE; - mpu_priv_flash(base, size); + /* Region 3, for FLASH area, default to set WBWA */ + mpu_user_intsram_wb(CONFIG_S5J_FLASH_BASE, CONFIG_S5J_FLASH_SIZE); - /* Region 5, for wifi dedicated area, RW-WBWA, 0x043C_0000 -- 8KB */ - mpu_user_intsram_wb(CONFIG_NVRAM_WIFI_START, 8 * 1024); + /* region 4, for Sflash Mirror area to be read only */ + mpu_priv_flash(CONFIG_S5J_FLASH_MIRROR_BASE, CONFIG_S5J_FLASH_SIZE); -#ifdef CONFIG_FS_SMARTFS - /* - * Region 6, FILE SYSTEM : 0x0440_0000 ++ 4MB - 256KB - * filesystem - smartfs - */ - base = CONFIG_S5J_FLASH_BASE + CONFIG_S5J_BOOTLOADER_REGION_SIZE; - size = CONFIG_S5J_FLASH_SIZE - CONFIG_S5J_BOOTLOADER_REGION_SIZE; - mpu_user_intsram_wb(base, size); -#endif + /* Region 5, for SFR area read/write, strongly-ordered */ + mpu_priv_stronglyordered(0x80000000, 0x10000000); /* - * Region 7, SSS F/W region2 : 0x047C_0000 ++ 256KB - * SSS key area RW, priority higher than 0x0400_0000, 4MB attribute(WBWA, RO) + * Region 6, for vector table, + * s5j uses high vector in 0xFFFF_0000++4KB, read only */ - base = CONFIG_S5J_FLASH_BASE + CONFIG_S5J_FLASH_SIZE; - size = 256 * 1024; - mpu_user_intsram_wb(base, size); - - /* region 8, for Sflash Mirror(0x6000_0000, RO) */ - mpu_priv_flash(0x60000000, CONFIG_S5J_FLASH_SIZE); - - /* Region 9, for vecotr table(0x8000_0000, RW-STRONG-ORDER */ - mpu_priv_stronglyordered(0x80000000, 0x10000000); - - /* Region 10, for vecotr table(0xFFFF_0000++4KB, RO-WT */ mpu_priv_flash(0xFFFF0000, 0x1000); mpu_control(true); - +#endif return 0; } #endif -- 2.7.4