From d0686a02b98ee264532c25108edc3ba44acc1145 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Thu, 8 Apr 2021 22:13:04 -0400 Subject: [PATCH] clk: k210: Fix PLLs not being enabled After starting or setting the rate of a PLL, the enable bit must be set. This fixes a bug where the AI ram would not be accessible, because it requires PLL1 to be running. Signed-off-by: Sean Anderson Reviewed-by: Damien Le Moal --- drivers/clk/kendryte/pll.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c index ab6d75d..f198920 100644 --- a/drivers/clk/kendryte/pll.c +++ b/drivers/clk/kendryte/pll.c @@ -531,6 +531,7 @@ static int k210_pll_enable(struct clk *clk) k210_pll_waitfor_lock(pll); reg &= ~K210_PLL_BYPASS; + reg |= K210_PLL_EN; writel(reg, pll->reg); return 0; @@ -550,6 +551,7 @@ static int k210_pll_disable(struct clk *clk) writel(reg, pll->reg); reg &= ~K210_PLL_PWRD; + reg &= ~K210_PLL_EN; writel(reg, pll->reg); return 0; } -- 2.7.4