From cff4e4140f0325e3f4097c71735f747682fd9eb5 Mon Sep 17 00:00:00 2001 From: Charles Baylis Date: Wed, 6 Dec 2017 15:19:42 +0000 Subject: [PATCH] [ARM] testsuite: force hardfp in addr-modes-float.c gcc/testsuite/ChangeLog: Charles Baylis * gcc.target/arm/addr-modes-float.c: Place dg-add-options after dg-require-effective-target. (ATTR): New define. (POST_STORE): Pass ATTR as 2nd argument. (POST_LOAD): Likewise. (POST_STORE_VEC): Likewise. * gcc.target/arm/addr-modes-int.c (ATTR): New define. (PRE_STORE): Pass ATTR as 2nd argument. (POST_STORE): Likewise. (PRE_LOAD): Likewise. (POST_LOAD): Likewise. * gcc.target/arm/addr-modes.h: (PRE_STORE): New parameter. (POST_STORE): Likewise. (POST_STORE_VEC): Likewise. (PRE_LOAD): Likewise. (POST_LOAD): Likewise. (POST_LOAD_VEC): Likewise. From-SVN: r255443 --- gcc/testsuite/ChangeLog | 20 ++++++++++++++ gcc/testsuite/gcc.target/arm/addr-modes-float.c | 28 +++++++++++--------- gcc/testsuite/gcc.target/arm/addr-modes-int.c | 35 ++++++++++++++----------- gcc/testsuite/gcc.target/arm/addr-modes.h | 30 ++++++++++----------- 4 files changed, 69 insertions(+), 44 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1ec2e94..e62aad4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,23 @@ +2017-12-06 Charles Baylis + + * gcc.target/arm/addr-modes-float.c: Place dg-add-options after + dg-require-effective-target. + (ATTR): New define. + (POST_STORE): Pass ATTR as 2nd argument. + (POST_LOAD): Likewise. + (POST_STORE_VEC): Likewise. + * gcc.target/arm/addr-modes-int.c (ATTR): New define. + (PRE_STORE): Pass ATTR as 2nd argument. + (POST_STORE): Likewise. + (PRE_LOAD): Likewise. + (POST_LOAD): Likewise. + * gcc.target/arm/addr-modes.h: (PRE_STORE): New parameter. + (POST_STORE): Likewise. + (POST_STORE_VEC): Likewise. + (PRE_LOAD): Likewise. + (POST_LOAD): Likewise. + (POST_LOAD_VEC): Likewise. + 2017-12-06 Jakub Jelinek PR tree-optimization/81945 diff --git a/gcc/testsuite/gcc.target/arm/addr-modes-float.c b/gcc/testsuite/gcc.target/arm/addr-modes-float.c index 3b4235c..5ffbcb1 100644 --- a/gcc/testsuite/gcc.target/arm/addr-modes-float.c +++ b/gcc/testsuite/gcc.target/arm/addr-modes-float.c @@ -1,41 +1,43 @@ /* { dg-options "-O2" } */ -/* { dg-add-options arm_neon } */ /* { dg-require-effective-target arm_neon_ok } */ +/* { dg-add-options arm_neon } */ /* { dg-do compile } */ #include #include "addr-modes.h" -POST_STORE(float) +#define ATTR __attribute__((__pcs__("aapcs-vfp"))) + +POST_STORE(float, ATTR) /* { dg-final { scan-assembler "vstmia.32" } } */ -POST_STORE(double) +POST_STORE(double, ATTR) /* { dg-final { scan-assembler "vstmia.64" } } */ -POST_LOAD(float) +POST_LOAD(float, ATTR) /* { dg-final { scan-assembler "vldmia.32" } } */ -POST_LOAD(double) +POST_LOAD(double, ATTR) /* { dg-final { scan-assembler "vldmia.64" } } */ -POST_STORE_VEC (int8_t, int8x8_t, vst1_s8) +POST_STORE_VEC (int8_t, int8x8_t, vst1_s8, ATTR) /* { dg-final { scan-assembler "vst1.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */ -POST_STORE_VEC (int8_t, int8x16_t, vst1q_s8) +POST_STORE_VEC (int8_t, int8x16_t, vst1q_s8, ATTR) /* { dg-final { scan-assembler "vst1.8\t\{.*\[-,\]d.*\}, \\\[r\[0-9\]+\\\]!" } } */ -POST_STORE_VEC (int8_t, int8x8x2_t, vst2_s8) +POST_STORE_VEC (int8_t, int8x8x2_t, vst2_s8, ATTR) /* { dg-final { scan-assembler "vst2.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */ -POST_STORE_VEC (int8_t, int8x16x2_t, vst2q_s8) +POST_STORE_VEC (int8_t, int8x16x2_t, vst2q_s8, ATTR) /* { dg-final { scan-assembler "vst2.8\t\{.*-d.*\}, \\\[r\[0-9\]+\\\]!" } } */ -POST_STORE_VEC (int8_t, int8x8x3_t, vst3_s8) +POST_STORE_VEC (int8_t, int8x8x3_t, vst3_s8, ATTR) /* { dg-final { scan-assembler "vst3.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */ -POST_STORE_VEC (int8_t, int8x16x3_t, vst3q_s8) +POST_STORE_VEC (int8_t, int8x16x3_t, vst3q_s8, ATTR) /* { dg-final { scan-assembler "vst3.8\t\{d\[02468\], d\[02468\], d\[02468\]\}, \\\[r\[0-9\]+\\\]!" } } */ /* { dg-final { scan-assembler "vst3.8\t\{d\[13579\], d\[13579\], d\[13579\]\}, \\\[r\[0-9\]+\\\]!" { xfail *-*-* } } } */ -POST_STORE_VEC (int8_t, int8x8x4_t, vst4_s8) +POST_STORE_VEC (int8_t, int8x8x4_t, vst4_s8, ATTR) /* { dg-final { scan-assembler "vst4.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */ -POST_STORE_VEC (int8_t, int8x16x4_t, vst4q_s8) +POST_STORE_VEC (int8_t, int8x16x4_t, vst4q_s8, ATTR) /* { dg-final { scan-assembler "vst4.8\t\{d\[02468\], d\[02468\], d\[02468\], d\[02468\]\}, \\\[r\[0-9\]+\\\]!" } } */ /* { dg-final { scan-assembler "vst4.8\t\{d\[13579\], d\[13579\], d\[13579\], d\[13579\]\}, \\\[r\[0-9\]+\\\]!" { xfail *-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/arm/addr-modes-int.c b/gcc/testsuite/gcc.target/arm/addr-modes-int.c index e3e1e6a..90b7425 100644 --- a/gcc/testsuite/gcc.target/arm/addr-modes-int.c +++ b/gcc/testsuite/gcc.target/arm/addr-modes-int.c @@ -7,40 +7,43 @@ typedef long long ll; -PRE_STORE(char) +/* no special function attribute required */ +#define ATTR /* */ + +PRE_STORE(char, ATTR) /* { dg-final { scan-assembler "strb.*#1]!" } } */ -PRE_STORE(short) +PRE_STORE(short, ATTR) /* { dg-final { scan-assembler "strh.*#2]!" } } */ -PRE_STORE(int) +PRE_STORE(int, ATTR) /* { dg-final { scan-assembler "str.*#4]!" } } */ -PRE_STORE(ll) +PRE_STORE(ll, ATTR) /* { dg-final { scan-assembler "strd.*#8]!" } } */ -POST_STORE(char) +POST_STORE(char, ATTR) /* { dg-final { scan-assembler "strb.*], #1" } } */ -POST_STORE(short) +POST_STORE(short, ATTR) /* { dg-final { scan-assembler "strh.*], #2" } } */ -POST_STORE(int) +POST_STORE(int, ATTR) /* { dg-final { scan-assembler "str.*], #4" } } */ -POST_STORE(ll) +POST_STORE(ll, ATTR) /* { dg-final { scan-assembler "strd.*], #8" } } */ -PRE_LOAD(char) +PRE_LOAD(char, ATTR) /* { dg-final { scan-assembler "ldrb.*#1]!" } } */ -PRE_LOAD(short) +PRE_LOAD(short, ATTR) /* { dg-final { scan-assembler "ldrsh.*#2]!" } } */ -PRE_LOAD(int) +PRE_LOAD(int, ATTR) /* { dg-final { scan-assembler "ldr.*#4]!" } } */ -PRE_LOAD(ll) +PRE_LOAD(ll, ATTR) /* { dg-final { scan-assembler "ldrd.*#8]!" } } */ -POST_LOAD(char) +POST_LOAD(char, ATTR) /* { dg-final { scan-assembler "ldrb.*], #1" } } */ -POST_LOAD(short) +POST_LOAD(short, ATTR) /* { dg-final { scan-assembler "ldrsh.*], #2" } } */ -POST_LOAD(int) +POST_LOAD(int, ATTR) /* { dg-final { scan-assembler "ldr.*], #4" } } */ -POST_LOAD(ll) +POST_LOAD(ll, ATTR) /* { dg-final { scan-assembler "ldrd.*], #8" } } */ /* { dg-final { scan-assembler-not "\tadd" } } */ diff --git a/gcc/testsuite/gcc.target/arm/addr-modes.h b/gcc/testsuite/gcc.target/arm/addr-modes.h index eac4678..9844c6a 100644 --- a/gcc/testsuite/gcc.target/arm/addr-modes.h +++ b/gcc/testsuite/gcc.target/arm/addr-modes.h @@ -1,22 +1,22 @@ -#define PRE_STORE(T) \ - T * \ +#define PRE_STORE(T, ATTR) \ + ATTR T * \ T ## _pre_store (T *p, T v) \ { \ *++p = v; \ return p; \ } \ -#define POST_STORE(T) \ - T * \ +#define POST_STORE(T, ATTR) \ + ATTR T * \ T ## _post_store (T *p, T v) \ { \ *p++ = v; \ return p; \ } -#define POST_STORE_VEC(T, VT, OP) \ - T * \ +#define POST_STORE_VEC(T, VT, OP, ATTR) \ + ATTR T * \ VT ## _post_store (T * p, VT v) \ { \ OP (p, v); \ @@ -24,29 +24,29 @@ return p; \ } -#define PRE_LOAD(T) \ - void \ +#define PRE_LOAD(T, ATTR) \ + ATTR void \ T ## _pre_load (T *p) \ { \ - extern void f ## T (T*,T); \ + ATTR extern void f ## T (T*,T); \ T x = *++p; \ f ## T (p, x); \ } -#define POST_LOAD(T) \ - void \ +#define POST_LOAD(T, ATTR) \ + ATTR void \ T ## _post_load (T *p) \ { \ - extern void f ## T (T*,T); \ + ATTR extern void f ## T (T*,T); \ T x = *p++; \ f ## T (p, x); \ } -#define POST_LOAD_VEC(T, VT, OP) \ - void \ +#define POST_LOAD_VEC(T, VT, OP, ATTR) \ + ATTR void \ VT ## _post_load (T * p) \ { \ - extern void f ## T (T*,T); \ + ATTR extern void f ## T (T*,T); \ VT x = OP (p, v); \ p += sizeof (VT) / sizeof (T); \ f ## T (p, x); \ -- 2.7.4