From cfec5ff1b95a3e74623f096f24367a3ef23dcb5c Mon Sep 17 00:00:00 2001 From: Reid Kleckner Date: Mon, 29 Aug 2016 16:35:43 +0000 Subject: [PATCH] Make vec_fabs.ll pass with MSVC 2013 We should revert this change once we drop support for MSVC 2013. llvm-svn: 279979 --- llvm/test/CodeGen/X86/vec_fabs.ll | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/llvm/test/CodeGen/X86/vec_fabs.ll b/llvm/test/CodeGen/X86/vec_fabs.ll index 9edb6ff..854b84c 100644 --- a/llvm/test/CodeGen/X86/vec_fabs.ll +++ b/llvm/test/CodeGen/X86/vec_fabs.ll @@ -6,6 +6,9 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefix=X64 --check-prefix=X64_AVX512VL ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=X64 --check-prefix=X64_AVX512VLDQ +; FIXME: Drop the regex pattern matching of 'nan' once we drop support for MSVC +; 2013. + define <2 x double> @fabs_v2f64(<2 x double> %p) { ; X32-LABEL: fabs_v2f64: ; X32: # BB#0: @@ -135,7 +138,7 @@ declare <8 x float> @llvm.fabs.v8f32(<8 x float> %p) define <8 x double> @fabs_v8f64(<8 x double> %p) { ; X32_AVX-LABEL: fabs_v8f64: ; X32_AVX: # BB#0: -; X32_AVX-NEXT: vmovaps {{.*#+}} ymm2 = [nan,nan,nan,nan] +; X32_AVX-NEXT: vmovaps {{.*#+}} ymm2 = [{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}}] ; X32_AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 ; X32_AVX-NEXT: vandps %ymm2, %ymm1, %ymm1 ; X32_AVX-NEXT: retl @@ -153,7 +156,7 @@ define <8 x double> @fabs_v8f64(<8 x double> %p) { ; ; X64_AVX-LABEL: fabs_v8f64: ; X64_AVX: # BB#0: -; X64_AVX-NEXT: vmovaps {{.*#+}} ymm2 = [nan,nan,nan,nan] +; X64_AVX-NEXT: vmovaps {{.*#+}} ymm2 = [{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}}] ; X64_AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 ; X64_AVX-NEXT: vandps %ymm2, %ymm1, %ymm1 ; X64_AVX-NEXT: retq @@ -176,7 +179,7 @@ declare <8 x double> @llvm.fabs.v8f64(<8 x double> %p) define <16 x float> @fabs_v16f32(<16 x float> %p) { ; X32_AVX-LABEL: fabs_v16f32: ; X32_AVX: # BB#0: -; X32_AVX-NEXT: vmovaps {{.*#+}} ymm2 = [nan,nan,nan,nan,nan,nan,nan,nan] +; X32_AVX-NEXT: vmovaps {{.*#+}} ymm2 = [{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}}] ; X32_AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 ; X32_AVX-NEXT: vandps %ymm2, %ymm1, %ymm1 ; X32_AVX-NEXT: retl @@ -194,7 +197,7 @@ define <16 x float> @fabs_v16f32(<16 x float> %p) { ; ; X64_AVX-LABEL: fabs_v16f32: ; X64_AVX: # BB#0: -; X64_AVX-NEXT: vmovaps {{.*#+}} ymm2 = [nan,nan,nan,nan,nan,nan,nan,nan] +; X64_AVX-NEXT: vmovaps {{.*#+}} ymm2 = [{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}},{{(nan|1\.#QNAN0e\+00)}}] ; X64_AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 ; X64_AVX-NEXT: vandps %ymm2, %ymm1, %ymm1 ; X64_AVX-NEXT: retq -- 2.7.4