From cf7d18b75c987fdb31bf1f55d1740055d8917327 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Fri, 29 Jul 2016 17:51:23 +0100 Subject: [PATCH] radeonsi: unify emitting PKT3_SET_BASE for indirect draws MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Marek Olšák --- src/gallium/drivers/radeonsi/si_state_draw.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index d743e22..523c2ea 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -591,8 +591,17 @@ static void si_emit_draw_packets(struct si_context *sctx, sctx->last_sh_base_reg = sh_base_reg; } } else { + uint64_t indirect_va = r600_resource(info->indirect)->gpu_address; + + assert(indirect_va % 8 == 0); + si_invalidate_draw_sh_constants(sctx); + radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0)); + radeon_emit(cs, 1); + radeon_emit(cs, indirect_va); + radeon_emit(cs, indirect_va >> 32); + radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, (struct r600_resource *)info->indirect, RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT); @@ -608,17 +617,9 @@ static void si_emit_draw_packets(struct si_context *sctx, RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER); if (info->indirect) { - uint64_t indirect_va = r600_resource(info->indirect)->gpu_address; - - assert(indirect_va % 8 == 0); assert(index_va % 2 == 0); assert(info->indirect_offset % 4 == 0); - radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0)); - radeon_emit(cs, 1); - radeon_emit(cs, indirect_va); - radeon_emit(cs, indirect_va >> 32); - radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0)); radeon_emit(cs, index_va); radeon_emit(cs, index_va >> 32); @@ -656,16 +657,8 @@ static void si_emit_draw_packets(struct si_context *sctx, } } else { if (info->indirect) { - uint64_t indirect_va = r600_resource(info->indirect)->gpu_address; - - assert(indirect_va % 8 == 0); assert(info->indirect_offset % 4 == 0); - radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0)); - radeon_emit(cs, 1); - radeon_emit(cs, indirect_va); - radeon_emit(cs, indirect_va >> 32); - if (sctx->b.family < CHIP_POLARIS10) { radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, render_cond_bit)); radeon_emit(cs, info->indirect_offset); -- 2.7.4