From cf6bdda3002dcda53633678c9dfec73ad7464386 Mon Sep 17 00:00:00 2001 From: "Zhengrong.Zhu" Date: Sat, 2 Nov 2019 10:01:55 +0800 Subject: [PATCH] hdmitx: Coverity defect cleanup: VOUT [1/1] PD#SWPL-13989 Problem: Coverity defect cleanup: VOUT Solution: Modify code according to coverity Verify: verify on the board of U212 Change-Id: I787429350be37da84ccd85332e97d472f45d3826 Signed-off-by: Zhengrong Zhu --- .../media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c | 28 +++------------------- 1 file changed, 3 insertions(+), 25 deletions(-) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c index de0e171..9de4c8c 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c @@ -1313,13 +1313,11 @@ static void hdmi_tvenc_vesa_set(struct hdmitx_vidpara *param) unsigned long hsync_pixels_venc = 0; unsigned long de_h_begin = 0, de_h_end = 0; - unsigned long de_v_begin_even = 0, de_v_end_even = 0, - de_v_begin_odd = 0, de_v_end_odd = 0; + unsigned long de_v_begin_even = 0, de_v_end_even = 0; unsigned long hs_begin = 0, hs_end = 0; unsigned long vs_adjust = 0; - unsigned long vs_bline_evn = 0, vs_eline_evn = 0, - vs_bline_odd = 0, vs_eline_odd = 0; - unsigned long vso_begin_evn = 0, vso_begin_odd = 0; + unsigned long vs_bline_evn = 0, vs_eline_evn = 0; + unsigned long vso_begin_evn = 0; struct hdmi_format_para *vpara = NULL; struct hdmi_cea_timing *vtiming = NULL; @@ -1370,15 +1368,6 @@ static void hdmi_tvenc_vesa_set(struct hdmitx_vidpara *param) de_v_end_even = de_v_begin_even + ACTIVE_LINES; hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even); hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); /* 522 */ - /* Program DE timing for odd field if needed */ - if (INTERLACE_MODE) { - de_v_begin_odd = to_signed( - (hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST) - & 0xf0)>>4) + de_v_begin_even + (TOTAL_LINES-1)/2; - de_v_end_odd = de_v_begin_odd + ACTIVE_LINES; - hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd); - hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd); - } /* Program Hsync timing */ if (de_h_end + front_porch_venc >= total_pixels_venc) { @@ -1404,17 +1393,6 @@ static void hdmi_tvenc_vesa_set(struct hdmitx_vidpara *param) vso_begin_evn = hs_begin; /* 1692 */ hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 1692 */ hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 1692 */ - /* Program Vsync timing for odd field if needed */ - if (INTERLACE_MODE) { - vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES; - vs_eline_odd = de_v_begin_odd-1 - SOF_LINES; - vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1), - total_pixels_venc); - hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd); - hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd); - hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd); - hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd); - } switch (param->VIC) { case HDMIV_640x480p60hz: -- 2.7.4