From cecac32a06a71bc27fbcc8b5491400836952302d Mon Sep 17 00:00:00 2001 From: Lars Poeschel Date: Wed, 3 Apr 2013 04:37:52 +0000 Subject: [PATCH] pcm051: Enable DDR PHY dynamic power down bit This is done already for am335x in 59dcf970d11ebff5d9f4bbbde79fda584e9e7ad4 and also applies for pcm051. It powers down the IO receiver when not performing read which helps reducing the overall power consuption in low power states (suspend/standby). Signed-off-by: Lars Poeschel --- board/phytec/pcm051/board.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 1708ac2..43d7b6e 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -104,7 +104,8 @@ static struct emif_regs ddr3_emif_reg_data = { .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2, .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3, .zq_config = MT41J256M8HX15E_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY, + .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, }; #endif -- 2.7.4