From cea862386791e281c4e9ab07dd118321f6655435 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 19 Apr 2019 23:54:46 +0300 Subject: [PATCH] ARM: dts: lpc32xx: add address and size cell values to SPI controller nodes All 4 SPI controllers on NXP LPC32xx SoC support SPI slaves discerning them by one cell address value, set it as default to avoid duplication in board device tree files. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-phy3250.dts | 2 -- arch/arm/boot/dts/lpc32xx.dtsi | 8 ++++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index b99726d..1b15f79 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -202,8 +202,6 @@ }; &ssp0 { - #address-cells = <1>; - #size-cells = <0>; num-cs = <1>; cs-gpios = <&gpio 3 5 0>; status = "okay"; diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index a0fedab..bc32450 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -187,6 +187,8 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SSP0>; clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -194,6 +196,8 @@ compatible = "nxp,lpc3220-spi"; reg = <0x20088000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI1>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -207,6 +211,8 @@ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SSP1>; clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -214,6 +220,8 @@ compatible = "nxp,lpc3220-spi"; reg = <0x20090000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI2>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; -- 2.7.4