From cea7c6969d777615b0a29584b1be4c90ea968944 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 27 Aug 2018 18:11:31 +0000 Subject: [PATCH] DAG: Check transformed type for forming fminnum/fmaxnum from vselect Follow up to r340655 to fix vector types which are split. llvm-svn: 340766 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 5 +++-- llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll | 28 ++++++--------------------- llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll | 28 ++++++--------------------- 3 files changed, 15 insertions(+), 46 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 44fdbc1b..0addc50 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -7040,6 +7040,7 @@ static SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS, if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True)) return SDValue(); + EVT TransformVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); switch (CC) { case ISD::SETOLT: case ISD::SETOLE: @@ -7048,7 +7049,7 @@ static SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS, case ISD::SETULT: case ISD::SETULE: { unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM; - if (TLI.isOperationLegalOrCustom(Opcode, VT)) + if (TLI.isOperationLegalOrCustom(Opcode, TransformVT)) return DAG.getNode(Opcode, DL, VT, LHS, RHS); return SDValue(); } @@ -7059,7 +7060,7 @@ static SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS, case ISD::SETUGT: case ISD::SETUGE: { unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM; - if (TLI.isOperationLegalOrCustom(Opcode, VT)) + if (TLI.isOperationLegalOrCustom(Opcode, TransformVT)) return DAG.getNode(Opcode, DL, VT, LHS, RHS); return SDValue(); } diff --git a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll index 755a46b..4563ec4 100644 --- a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll @@ -153,11 +153,8 @@ define <3 x half> @test_fmax_legacy_ugt_v3f16(<3 x half> %a, <3 x half> %b) #0 { ; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_v3f16: ; GFX9-NNAN: ; %bb.0: ; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NNAN-NEXT: v_max_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX9-NNAN-NEXT: v_max_f16_e32 v0, v0, v2 -; GFX9-NNAN-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX9-NNAN-NEXT: v_max_f16_e32 v1, v1, v3 -; GFX9-NNAN-NEXT: v_lshl_or_b32 v0, v4, 16, v0 +; GFX9-NNAN-NEXT: v_pk_max_f16 v1, v1, v3 +; GFX9-NNAN-NEXT: v_pk_max_f16 v0, v0, v2 ; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31] ; ; VI-SAFE-LABEL: test_fmax_legacy_ugt_v3f16: @@ -414,23 +411,10 @@ define <8 x half> @test_fmax_legacy_ugt_v8f16(<8 x half> %a, <8 x half> %b) #0 { ; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_v8f16: ; GFX9-NNAN: ; %bb.0: ; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NNAN-NEXT: v_max_f16_sdwa v8, v3, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX9-NNAN-NEXT: v_max_f16_sdwa v9, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX9-NNAN-NEXT: v_max_f16_sdwa v10, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX9-NNAN-NEXT: v_max_f16_sdwa v11, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX9-NNAN-NEXT: v_max_f16_e32 v0, v0, v4 -; GFX9-NNAN-NEXT: v_mov_b32_e32 v4, 0xffff -; GFX9-NNAN-NEXT: v_max_f16_e32 v3, v3, v7 -; GFX9-NNAN-NEXT: v_max_f16_e32 v2, v2, v6 -; GFX9-NNAN-NEXT: v_max_f16_e32 v1, v1, v5 -; GFX9-NNAN-NEXT: v_and_b32_e32 v0, v4, v0 -; GFX9-NNAN-NEXT: v_and_b32_e32 v1, v4, v1 -; GFX9-NNAN-NEXT: v_and_b32_e32 v2, v4, v2 -; GFX9-NNAN-NEXT: v_and_b32_e32 v3, v4, v3 -; GFX9-NNAN-NEXT: v_lshl_or_b32 v0, v11, 16, v0 -; GFX9-NNAN-NEXT: v_lshl_or_b32 v1, v10, 16, v1 -; GFX9-NNAN-NEXT: v_lshl_or_b32 v2, v9, 16, v2 -; GFX9-NNAN-NEXT: v_lshl_or_b32 v3, v8, 16, v3 +; GFX9-NNAN-NEXT: v_pk_max_f16 v0, v0, v4 +; GFX9-NNAN-NEXT: v_pk_max_f16 v1, v1, v5 +; GFX9-NNAN-NEXT: v_pk_max_f16 v2, v2, v6 +; GFX9-NNAN-NEXT: v_pk_max_f16 v3, v3, v7 ; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31] ; ; VI-SAFE-LABEL: test_fmax_legacy_ugt_v8f16: diff --git a/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll b/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll index 9ad2bd4..58c70c0 100644 --- a/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll @@ -154,11 +154,8 @@ define <3 x half> @test_fmin_legacy_ule_v3f16(<3 x half> %a, <3 x half> %b) #0 { ; GFX9-NNAN-LABEL: test_fmin_legacy_ule_v3f16: ; GFX9-NNAN: ; %bb.0: ; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NNAN-NEXT: v_min_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX9-NNAN-NEXT: v_min_f16_e32 v0, v0, v2 -; GFX9-NNAN-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX9-NNAN-NEXT: v_min_f16_e32 v1, v1, v3 -; GFX9-NNAN-NEXT: v_lshl_or_b32 v0, v4, 16, v0 +; GFX9-NNAN-NEXT: v_pk_min_f16 v1, v1, v3 +; GFX9-NNAN-NEXT: v_pk_min_f16 v0, v0, v2 ; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31] ; ; VI-SAFE-LABEL: test_fmin_legacy_ule_v3f16: @@ -415,23 +412,10 @@ define <8 x half> @test_fmin_legacy_ule_v8f16(<8 x half> %a, <8 x half> %b) #0 { ; GFX9-NNAN-LABEL: test_fmin_legacy_ule_v8f16: ; GFX9-NNAN: ; %bb.0: ; GFX9-NNAN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NNAN-NEXT: v_min_f16_sdwa v8, v3, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX9-NNAN-NEXT: v_min_f16_sdwa v9, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX9-NNAN-NEXT: v_min_f16_sdwa v10, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX9-NNAN-NEXT: v_min_f16_sdwa v11, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX9-NNAN-NEXT: v_min_f16_e32 v0, v0, v4 -; GFX9-NNAN-NEXT: v_mov_b32_e32 v4, 0xffff -; GFX9-NNAN-NEXT: v_min_f16_e32 v3, v3, v7 -; GFX9-NNAN-NEXT: v_min_f16_e32 v2, v2, v6 -; GFX9-NNAN-NEXT: v_min_f16_e32 v1, v1, v5 -; GFX9-NNAN-NEXT: v_and_b32_e32 v0, v4, v0 -; GFX9-NNAN-NEXT: v_and_b32_e32 v1, v4, v1 -; GFX9-NNAN-NEXT: v_and_b32_e32 v2, v4, v2 -; GFX9-NNAN-NEXT: v_and_b32_e32 v3, v4, v3 -; GFX9-NNAN-NEXT: v_lshl_or_b32 v0, v11, 16, v0 -; GFX9-NNAN-NEXT: v_lshl_or_b32 v1, v10, 16, v1 -; GFX9-NNAN-NEXT: v_lshl_or_b32 v2, v9, 16, v2 -; GFX9-NNAN-NEXT: v_lshl_or_b32 v3, v8, 16, v3 +; GFX9-NNAN-NEXT: v_pk_min_f16 v0, v0, v4 +; GFX9-NNAN-NEXT: v_pk_min_f16 v1, v1, v5 +; GFX9-NNAN-NEXT: v_pk_min_f16 v2, v2, v6 +; GFX9-NNAN-NEXT: v_pk_min_f16 v3, v3, v7 ; GFX9-NNAN-NEXT: s_setpc_b64 s[30:31] ; ; VI-SAFE-LABEL: test_fmin_legacy_ule_v8f16: -- 2.7.4