From ce2486ab207e98f04931bc0f562ed4807258344a Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 22 Jun 2011 04:21:29 +0000 Subject: [PATCH] sim: bfin: pass up result2/errcode with libgloss syscalls Now that the Blackfin libgloss code extracts the 2nd result and the error code from the R1/R2 registers, have the sim fill them up. Signed-off-by: Mike Frysinger --- sim/bfin/ChangeLog | 5 +++++ sim/bfin/interp.c | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index 92d968a..a504f7a 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,3 +1,8 @@ +2011-06-22 Mike Frysinger + + * interp.c (bfin_syscall): Delete old comment. Set dreg 1 to + sc.result2 and dreg 2 to sc.errcode. + 2011-06-18 Robin Getz * bfin-sim.c (decode_dsp32shift_0): Clear ASTAT[AV] if val is 0, diff --git a/sim/bfin/interp.c b/sim/bfin/interp.c index d0a4e22..583b82e 100644 --- a/sim/bfin/interp.c +++ b/sim/bfin/interp.c @@ -594,8 +594,8 @@ bfin_syscall (SIM_CPU *cpu) { tbuf += sprintf (tbuf, "%lu (error = %i)", sc.result, sc.errcode); SET_DREG (0, sc.result); - /* Blackfin libgloss only expects R0 to be updated, not R1. */ - /*SET_DREG (1, sc.errcode);*/ + SET_DREG (1, sc.result2); + SET_DREG (2, sc.errcode); } TRACE_SYSCALL (cpu, "%s", _tbuf); -- 2.7.4