From cdee88a2e061d529f442a0d01a18ed0688fc207a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 18 Jul 2023 09:34:25 -0700 Subject: [PATCH] [RISCV] Add isMoveReg to vmv1r/vmv2r/vmv4r/vmv8r.v. This allows TII isCopyInstrImpl to consider them copies. Reviewed By: wangpc Differential Revision: https://reviews.llvm.org/D155140 --- llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 2 +- llvm/test/CodeGen/RISCV/rvv/copyprop.mir | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index 6cf3dbd..6e5ee80 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -1683,7 +1683,7 @@ let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in { defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>; } // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress -let hasSideEffects = 0, mayLoad = 0, mayStore = 0, +let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1, RVVConstraint = NoConstraint in { // A future extension may relax the vector register alignment restrictions. foreach n = [1, 2, 4, 8] in { diff --git a/llvm/test/CodeGen/RISCV/rvv/copyprop.mir b/llvm/test/CodeGen/RISCV/rvv/copyprop.mir index 7c94299..eb4c8bf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/copyprop.mir +++ b/llvm/test/CodeGen/RISCV/rvv/copyprop.mir @@ -23,8 +23,7 @@ ; CHECK-NEXT: li a2, 128 ; CHECK-NEXT: bgeu a0, a2, .LBB0_2 ; CHECK-NEXT: .LBB0_4: # %entry - ; CHECK-NEXT: vmv1r.v v8, v9 - ; CHECK-NEXT: vse64.v v8, (a1) + ; CHECK-NEXT: vse64.v v9, (a1) ; CHECK-NEXT: ret entry: ret void -- 2.7.4