From cd76fa79b01aef8afe219323f713ca1607d7a98f Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Fri, 8 Oct 2021 16:30:55 -0400 Subject: [PATCH] [InstCombine] add tests for icmp of negated op; NFC --- llvm/test/Transforms/InstCombine/icmp-sub.ll | 283 +++++++++++++++++++++++++++ 1 file changed, 283 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/icmp-sub.ll b/llvm/test/Transforms/InstCombine/icmp-sub.ll index 5f12270..4fa31be 100644 --- a/llvm/test/Transforms/InstCombine/icmp-sub.ll +++ b/llvm/test/Transforms/InstCombine/icmp-sub.ll @@ -1,6 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s +declare void @use(i32) +declare void @use_vec(<2 x i8>) + define i1 @test_nuw_and_unsigned_pred(i64 %x) { ; CHECK-LABEL: @test_nuw_and_unsigned_pred( ; CHECK-NEXT: [[Z:%.*]] = icmp ugt i64 [[X:%.*]], 7 @@ -185,3 +188,283 @@ define <2 x i1> @icmp_eq_sub_non_splat2(<2 x i32> %a) { %cmp = icmp eq <2 x i32> %sub, ret <2 x i1> %cmp } + +define i1 @neg_sgt_42(i32 %x) { +; CHECK-LABEL: @neg_sgt_42( +; CHECK-NEXT: [[NEGX:%.*]] = sub i32 0, [[X:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[NEGX]], 42 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub i32 0, %x + %r = icmp sgt i32 %negx, 42 + ret i1 %r +} + +define i1 @neg_eq_43(i32 %x) { +; CHECK-LABEL: @neg_eq_43( +; CHECK-NEXT: [[NEGX:%.*]] = sub i32 0, [[X:%.*]] +; CHECK-NEXT: call void @use(i32 [[NEGX]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[NEGX]], 43 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub i32 0, %x + call void @use(i32 %negx) + %r = icmp eq i32 %negx, 43 + ret i1 %r +} + +define i1 @neg_ne_44(i32 %x) { +; CHECK-LABEL: @neg_ne_44( +; CHECK-NEXT: [[NEGX:%.*]] = sub i32 0, [[X:%.*]] +; CHECK-NEXT: call void @use(i32 [[NEGX]]) +; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[NEGX]], 44 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub i32 0, %x + call void @use(i32 %negx) + %r = icmp ne i32 %negx, 44 + ret i1 %r +} + +define i1 @neg_nsw_eq_45(i32 %x) { +; CHECK-LABEL: @neg_nsw_eq_45( +; CHECK-NEXT: [[NEGX:%.*]] = sub nsw i32 0, [[X:%.*]] +; CHECK-NEXT: call void @use(i32 [[NEGX]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[NEGX]], 45 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub nsw i32 0, %x + call void @use(i32 %negx) + %r = icmp eq i32 %negx, 45 + ret i1 %r +} + +define i1 @neg_nsw_ne_46(i32 %x) { +; CHECK-LABEL: @neg_nsw_ne_46( +; CHECK-NEXT: [[NEGX:%.*]] = sub nsw i32 0, [[X:%.*]] +; CHECK-NEXT: call void @use(i32 [[NEGX]]) +; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[NEGX]], 46 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub nsw i32 0, %x + call void @use(i32 %negx) + %r = icmp ne i32 %negx, 46 + ret i1 %r +} + +define i1 @subC_eq(i32 %x) { +; CHECK-LABEL: @subC_eq( +; CHECK-NEXT: [[SUBX:%.*]] = sub i32 -2147483648, [[X:%.*]] +; CHECK-NEXT: call void @use(i32 [[SUBX]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[SUBX]], 43 +; CHECK-NEXT: ret i1 [[R]] +; + %subx = sub i32 -2147483648, %x + call void @use(i32 %subx) + %r = icmp eq i32 %subx, 43 + ret i1 %r +} + +define <2 x i1> @subC_ne(<2 x i8> %x) { +; CHECK-LABEL: @subC_ne( +; CHECK-NEXT: [[SUBX:%.*]] = sub <2 x i8> , [[X:%.*]] +; CHECK-NEXT: call void @use_vec(<2 x i8> [[SUBX]]) +; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i8> [[SUBX]], +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %subx = sub <2 x i8> , %x + call void @use_vec(<2 x i8> %subx) + %r = icmp ne <2 x i8> %subx, + ret <2 x i1> %r +} + +define i1 @subC_nsw_eq(i32 %x) { +; CHECK-LABEL: @subC_nsw_eq( +; CHECK-NEXT: [[SUBX:%.*]] = sub nsw i32 -100, [[X:%.*]] +; CHECK-NEXT: call void @use(i32 [[SUBX]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[SUBX]], -2147483648 +; CHECK-NEXT: ret i1 [[R]] +; + %subx = sub nsw i32 -100, %x + call void @use(i32 %subx) + %r = icmp eq i32 %subx, -2147483648 + ret i1 %r +} + +define i1 @subC_nsw_ne(i32 %x) { +; CHECK-LABEL: @subC_nsw_ne( +; CHECK-NEXT: [[SUBX:%.*]] = sub nsw i32 -2147483647, [[X:%.*]] +; CHECK-NEXT: call void @use(i32 [[SUBX]]) +; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[SUBX]], 46 +; CHECK-NEXT: ret i1 [[R]] +; + %subx = sub nsw i32 -2147483647, %x + call void @use(i32 %subx) + %r = icmp ne i32 %subx, 46 + ret i1 %r +} + +define i1 @neg_slt_42(i128 %x) { +; CHECK-LABEL: @neg_slt_42( +; CHECK-NEXT: [[NEGX:%.*]] = sub i128 0, [[X:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp slt i128 [[NEGX]], 42 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub i128 0, %x + %r = icmp slt i128 %negx, 42 + ret i1 %r +} + +define <2 x i1> @neg_ugt_42_splat(<2 x i7> %x) { +; CHECK-LABEL: @neg_ugt_42_splat( +; CHECK-NEXT: [[NEGX:%.*]] = sub <2 x i7> zeroinitializer, [[X:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ugt <2 x i7> [[NEGX]], +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %negx = sub <2 x i7> zeroinitializer, %x + %r = icmp ugt <2 x i7> %negx, + ret <2 x i1> %r +} + +define i1 @neg_sgt_42_use(i32 %x) { +; CHECK-LABEL: @neg_sgt_42_use( +; CHECK-NEXT: [[NEGX:%.*]] = sub i32 0, [[X:%.*]] +; CHECK-NEXT: call void @use(i32 [[NEGX]]) +; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[NEGX]], 42 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub i32 0, %x + call void @use(i32 %negx) + %r = icmp sgt i32 %negx, 42 + ret i1 %r +} + +; Test common/edge cases with signed pred. + +define i1 @neg_slt_n1(i8 %x) { +; CHECK-LABEL: @neg_slt_n1( +; CHECK-NEXT: [[NEGX:%.*]] = sub i8 0, [[X:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[NEGX]], -1 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub i8 0, %x + %r = icmp slt i8 %negx, -1 + ret i1 %r +} + +define i1 @neg_slt_0(i8 %x) { +; CHECK-LABEL: @neg_slt_0( +; CHECK-NEXT: [[NEGX:%.*]] = sub i8 0, [[X:%.*]] +; CHECK-NEXT: [[ISNEGNEG:%.*]] = icmp slt i8 [[NEGX]], 0 +; CHECK-NEXT: ret i1 [[ISNEGNEG]] +; + %negx = sub i8 0, %x + %isnegneg = icmp slt i8 %negx, 0 + ret i1 %isnegneg +} + +define i1 @neg_slt_1(i8 %x) { +; CHECK-LABEL: @neg_slt_1( +; CHECK-NEXT: [[NEGX:%.*]] = sub i8 0, [[X:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[NEGX]], 1 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub i8 0, %x + %r = icmp slt i8 %negx, 1 + ret i1 %r +} + +define i1 @neg_sgt_n1(i8 %x) { +; CHECK-LABEL: @neg_sgt_n1( +; CHECK-NEXT: [[NEGX:%.*]] = sub i8 0, [[X:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt i8 [[NEGX]], -1 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub i8 0, %x + %r = icmp sgt i8 %negx, -1 + ret i1 %r +} + +define i1 @neg_sgt_0(i8 %x) { +; CHECK-LABEL: @neg_sgt_0( +; CHECK-NEXT: [[NEGX:%.*]] = sub i8 0, [[X:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt i8 [[NEGX]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub i8 0, %x + %r = icmp sgt i8 %negx, 0 + ret i1 %r +} + +define i1 @neg_sgt_1(i8 %x) { +; CHECK-LABEL: @neg_sgt_1( +; CHECK-NEXT: [[NEGX:%.*]] = sub i8 0, [[X:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt i8 [[NEGX]], 1 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub i8 0, %x + %r = icmp sgt i8 %negx, 1 + ret i1 %r +} + +; Test common/edge cases with signed pred and nsw. + +define i1 @neg_nsw_slt_n1(i8 %x) { +; CHECK-LABEL: @neg_nsw_slt_n1( +; CHECK-NEXT: [[R:%.*]] = icmp sgt i8 [[X:%.*]], 1 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub nsw i8 0, %x + %r = icmp slt i8 %negx, -1 + ret i1 %r +} + +define i1 @neg_nsw_slt_0(i8 %x) { +; CHECK-LABEL: @neg_nsw_slt_0( +; CHECK-NEXT: [[ISNEGNEG:%.*]] = icmp sgt i8 [[X:%.*]], 0 +; CHECK-NEXT: ret i1 [[ISNEGNEG]] +; + %negx = sub nsw i8 0, %x + %isnegneg = icmp slt i8 %negx, 0 + ret i1 %isnegneg +} + +define i1 @neg_nsw_slt_1(i8 %x) { +; CHECK-LABEL: @neg_nsw_slt_1( +; CHECK-NEXT: [[R:%.*]] = icmp sgt i8 [[X:%.*]], -1 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub nsw i8 0, %x + %r = icmp slt i8 %negx, 1 + ret i1 %r +} + +define i1 @neg_nsw_sgt_n1(i8 %x) { +; CHECK-LABEL: @neg_nsw_sgt_n1( +; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[X:%.*]], 1 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub nsw i8 0, %x + %r = icmp sgt i8 %negx, -1 + ret i1 %r +} + +define i1 @neg_nsw_sgt_0(i8 %x) { +; CHECK-LABEL: @neg_nsw_sgt_0( +; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[X:%.*]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub nsw i8 0, %x + %r = icmp sgt i8 %negx, 0 + ret i1 %r +} + +define i1 @neg_nsw_sgt_1(i8 %x) { +; CHECK-LABEL: @neg_nsw_sgt_1( +; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[X:%.*]], -1 +; CHECK-NEXT: ret i1 [[R]] +; + %negx = sub nsw i8 0, %x + %r = icmp sgt i8 %negx, 1 + ret i1 %r +} -- 2.7.4