From cd5c4cb7e0aea8beffe9642c9202f677fff59ca0 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Fri, 17 Jun 2022 17:32:51 +0800 Subject: [PATCH] [RISCV] Add SiFive extension support Add SiFive extension support Depends on D147934 Differential Revision: https://reviews.llvm.org/D147935 --- clang/include/clang/Support/RISCVVIntrinsicUtils.h | 3 ++- clang/utils/TableGen/RISCVVEmitter.cpp | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h index bf31dced98b2..1a626e6a776a 100644 --- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h +++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h @@ -462,8 +462,9 @@ enum RVVRequire : uint8_t { RVV_REQ_None = 0, RVV_REQ_RV64 = 1 << 0, RVV_REQ_FullMultiply = 1 << 1, + RVV_REQ_Xsfvcp = 1 << 2, - LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_FullMultiply) + LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Xsfvcp) }; // Raw RVV intrinsic info, used to expand later. diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index 365fa8a67ffa..6228e0256d54 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -633,6 +633,7 @@ void RVVEmitter::createRVVIntrinsics( RVVRequire RequireExt = StringSwitch(RequiredFeature) .Case("RV64", RVV_REQ_RV64) .Case("FullMultiply", RVV_REQ_FullMultiply) + .Case("Xsfvcp", RVV_REQ_Xsfvcp) .Default(RVV_REQ_None); assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?"); SR.RequiredExtensions |= RequireExt; -- 2.34.1