From cd4bc4257f4401cddf46a5449d685eabee681e31 Mon Sep 17 00:00:00 2001 From: Leonard Mai Date: Mon, 28 Nov 2011 08:15:32 -0800 Subject: [PATCH] mrst: add cpu detection and earlyprintk support for cloverview BZ: 15575 Cloverview SOC use CPUID=0x30650 which translates x86_model to 0x35. The Medfield kernel currently does not support this x86_model number hence it won't be able to detect Cloverview SOC properly. Also, there is a memory map change on Cloverview's SPI1 interface hence earlyprintk won't work on Cloverview SOC. This patch adds CPU detection and earlyprintk support for Cloverview SOC. Change-Id: I1ce935aeee4b42a02b62e14c01682806d16e0acb Signed-off-by: Leonard D Mai Reviewed-by: Pierre Tardy Reviewed-by: Yong Yao Tested-by: Siva Prasath Ponnusamy Reviewed-on: http://android.intel.com:8080/25443 Reviewed-by: Gross, Mark Tested-by: Seibel, Eric Reviewed-by: buildbot Tested-by: buildbot --- arch/x86/include/asm/mrst.h | 1 + arch/x86/platform/mrst/early_printk_mrst.c | 3 +++ arch/x86/platform/mrst/mrst.c | 8 ++++---- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/mrst.h b/arch/x86/include/asm/mrst.h index 3c58c49..300154b 100644 --- a/arch/x86/include/asm/mrst.h +++ b/arch/x86/include/asm/mrst.h @@ -29,6 +29,7 @@ extern struct sfi_rtc_table_entry sfi_mrtc_array[]; enum mrst_cpu_type { MRST_CPU_CHIP_LINCROFT = 1, MRST_CPU_CHIP_PENWELL, + MRST_CPU_CHIP_CLOVERVIEW, }; extern enum mrst_cpu_type __mrst_cpu_chip; diff --git a/arch/x86/platform/mrst/early_printk_mrst.c b/arch/x86/platform/mrst/early_printk_mrst.c index 25bfdbb..b3b6494 100644 --- a/arch/x86/platform/mrst/early_printk_mrst.c +++ b/arch/x86/platform/mrst/early_printk_mrst.c @@ -32,6 +32,7 @@ #define MRST_SPI_TIMEOUT 0x200000 #define MRST_REGBASE_SPI0 0xff128000 #define MRST_REGBASE_SPI1 0xff128400 +#define CLV_REGBASE_SPI1 0xff135000 #define MRST_CLK_SPI0_REG 0xff11d86c /* Bit fields in CTRLR0 */ @@ -157,6 +158,8 @@ void mrst_early_console_init(void) if (mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL) mrst_spi_paddr = MRST_REGBASE_SPI1; + else if (mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW) + mrst_spi_paddr = CLV_REGBASE_SPI1; pspi = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE, mrst_spi_paddr); diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c index bda8157..8c594c1 100644 --- a/arch/x86/platform/mrst/mrst.c +++ b/arch/x86/platform/mrst/mrst.c @@ -236,7 +236,8 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table) static unsigned long __init mrst_calibrate_tsc(void) { unsigned long flags, fast_calibrate; - if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) { + if ((__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) || + (__mrst_cpu_chip == MRST_CPU_CHIP_CLOVERVIEW)) { u32 lo, hi, ratio, fsb; rdmsr(MSR_IA32_PERF_STATUS, lo, hi); @@ -298,14 +299,13 @@ static void __cpuinit mrst_arch_setup(void) __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL; else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26) __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT; + else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x35) + __mrst_cpu_chip = MRST_CPU_CHIP_CLOVERVIEW; else { pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n", boot_cpu_data.x86, boot_cpu_data.x86_model); __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT; } - pr_debug("Moorestown CPU %s identified\n", - (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ? - "Lincroft" : "Penwell"); } /* MID systems don't have i8042 controller */ -- 2.7.4