From cce43f6d8c40222099badaf52344d6a0eed993f3 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Tue, 14 Mar 2017 21:46:54 +0100 Subject: [PATCH] radv: Emit cache flushes before CP DMA. The flushes could be due to TRANSFER barriers. Signed-off-by: Bas Nieuwenhuizen Cc: 17.0 Reviewed-by: Dave Airlie --- src/amd/vulkan/si_cmd_buffer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 5d35287..b808052 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -998,6 +998,7 @@ void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer, uint64_t main_src_va, main_dest_va; uint64_t skipped_size = 0, realign_size = 0; + si_emit_cache_flush(cmd_buffer); if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO || cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) { @@ -1061,6 +1062,8 @@ void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va, assert(va % 4 == 0 && size % 4 == 0); + si_emit_cache_flush(cmd_buffer); + while (size) { unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT); unsigned dma_flags = 0; -- 2.7.4