From cca44b1b87795e0a92ec8d016456941a7986d107 Mon Sep 17 00:00:00 2001 From: Julian Brown Date: Thu, 30 Jul 2009 23:05:05 +0000 Subject: [PATCH] * arm-linux-tdep.c (arch-utils.h, inferior.h, gdbthread.h, symfile.h): Include files. (arm_linux_cleanup_svc, arm_linux_copy_svc): New. (cleanup_kernel_helper_return, arm_catch_kernel_helper_return): New. (arm_linux_displaced_step_copy_insn): New. (arm_linux_init_abi): Initialise displaced stepping callbacks. * arm-tdep.c (DISPLACED_STEPPING_ARCH_VERSION): New macro. (ARM_NOP): New. (displaced_read_reg, displaced_in_arm_mode, branch_write_pc) (bx_write_pc, load_write_pc, alu_write_pc, displaced_write_reg) (insn_references_pc, copy_unmodified, cleanup_preload, copy_preload) (copy_preload_reg, cleanup_copro_load_store, copy_copro_load_store) (cleanup_branch, copy_b_bl_blx, copy_bx_blx_reg, cleanup_alu_imm) (copy_alu_imm, cleanup_alu_reg, copy_alu_reg) (cleanup_alu_shifted_reg, copy_alu_shifted_reg, cleanup_load) (cleanup_store, copy_extra_ld_st, copy_ldr_str_ldrb_strb) (cleanup_block_load_all, cleanup_block_store_pc) (cleanup_block_load_pc, copy_block_xfer, cleanup_svc, copy_svc) (copy_undef, copy_unpred): New. (decode_misc_memhint_neon, decode_unconditional) (decode_miscellaneous, decode_dp_misc, decode_ld_st_word_ubyte) (decode_media, decode_b_bl_ldmstm, decode_ext_reg_ld_st) (decode_svc_copro, arm_process_displaced_insn) (arm_displaced_init_closure, arm_displaced_step_copy_insn) (arm_displaced_step_fixup): New. (arm_gdbarch_init): Initialise max insn length field. * arm-tdep.h (DISPLACED_TEMPS, DISPLACED_MODIFIED_INSNS): New macros. (displaced_step_closure, pc_write_style): New. (arm_displaced_init_closure, displaced_read_reg) (arm_process_displaced_insn, arm_displaced_init_closure) (displaced_read_reg, displaced_write_reg, arm_displaced_step_copy_insn) (arm_displaced_step_fixup): Add prototypes. --- gdb/ChangeLog | 36 + gdb/arm-linux-tdep.c | 216 +++++ gdb/arm-tdep.c | 2284 +++++++++++++++++++++++++++++++++++++++++++++----- gdb/arm-tdep.h | 102 +++ 4 files changed, 2426 insertions(+), 212 deletions(-) diff --git a/gdb/ChangeLog b/gdb/ChangeLog index b5f5167..9677954 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,39 @@ +2009-07-31 Julian Brown + + * arm-linux-tdep.c (arch-utils.h, inferior.h, gdbthread.h, symfile.h): + Include files. + (arm_linux_cleanup_svc, arm_linux_copy_svc): New. + (cleanup_kernel_helper_return, arm_catch_kernel_helper_return): New. + (arm_linux_displaced_step_copy_insn): New. + (arm_linux_init_abi): Initialise displaced stepping callbacks. + * arm-tdep.c (DISPLACED_STEPPING_ARCH_VERSION): New macro. + (ARM_NOP): New. + (displaced_read_reg, displaced_in_arm_mode, branch_write_pc) + (bx_write_pc, load_write_pc, alu_write_pc, displaced_write_reg) + (insn_references_pc, copy_unmodified, cleanup_preload, copy_preload) + (copy_preload_reg, cleanup_copro_load_store, copy_copro_load_store) + (cleanup_branch, copy_b_bl_blx, copy_bx_blx_reg, cleanup_alu_imm) + (copy_alu_imm, cleanup_alu_reg, copy_alu_reg) + (cleanup_alu_shifted_reg, copy_alu_shifted_reg, cleanup_load) + (cleanup_store, copy_extra_ld_st, copy_ldr_str_ldrb_strb) + (cleanup_block_load_all, cleanup_block_store_pc) + (cleanup_block_load_pc, copy_block_xfer, cleanup_svc, copy_svc) + (copy_undef, copy_unpred): New. + (decode_misc_memhint_neon, decode_unconditional) + (decode_miscellaneous, decode_dp_misc, decode_ld_st_word_ubyte) + (decode_media, decode_b_bl_ldmstm, decode_ext_reg_ld_st) + (decode_svc_copro, arm_process_displaced_insn) + (arm_displaced_init_closure, arm_displaced_step_copy_insn) + (arm_displaced_step_fixup): New. + (arm_gdbarch_init): Initialise max insn length field. + * arm-tdep.h (DISPLACED_TEMPS, DISPLACED_MODIFIED_INSNS): New + macros. + (displaced_step_closure, pc_write_style): New. + (arm_displaced_init_closure, displaced_read_reg) + (arm_process_displaced_insn, arm_displaced_init_closure) + (displaced_read_reg, displaced_write_reg, arm_displaced_step_copy_insn) + (arm_displaced_step_fixup): Add prototypes. + 2009-07-31 Pedro Alves Julian Brown diff --git a/gdb/arm-linux-tdep.c b/gdb/arm-linux-tdep.c index 20419cb..beb4ecf 100644 --- a/gdb/arm-linux-tdep.c +++ b/gdb/arm-linux-tdep.c @@ -38,6 +38,10 @@ #include "arm-linux-tdep.h" #include "linux-tdep.h" #include "glibc-tdep.h" +#include "arch-utils.h" +#include "inferior.h" +#include "gdbthread.h" +#include "symfile.h" #include "gdb_string.h" @@ -597,6 +601,210 @@ arm_linux_software_single_step (struct frame_info *frame) return 1; } +/* Support for displaced stepping of Linux SVC instructions. */ + +static void +arm_linux_cleanup_svc (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, + struct regcache *regs, + struct displaced_step_closure *dsc) +{ + CORE_ADDR from = dsc->insn_addr; + ULONGEST apparent_pc; + int within_scratch; + + regcache_cooked_read_unsigned (regs, ARM_PC_REGNUM, &apparent_pc); + + within_scratch = (apparent_pc >= dsc->scratch_base + && apparent_pc < (dsc->scratch_base + + DISPLACED_MODIFIED_INSNS * 4 + 4)); + + if (debug_displaced) + { + fprintf_unfiltered (gdb_stdlog, "displaced: PC is apparently %.8lx after " + "SVC step ", (unsigned long) apparent_pc); + if (within_scratch) + fprintf_unfiltered (gdb_stdlog, "(within scratch space)\n"); + else + fprintf_unfiltered (gdb_stdlog, "(outside scratch space)\n"); + } + + if (within_scratch) + displaced_write_reg (regs, dsc, ARM_PC_REGNUM, from + 4, BRANCH_WRITE_PC); +} + +static int +arm_linux_copy_svc (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to, + struct regcache *regs, struct displaced_step_closure *dsc) +{ + CORE_ADDR from = dsc->insn_addr; + struct frame_info *frame; + unsigned int svc_number = displaced_read_reg (regs, from, 7); + + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: copying Linux svc insn %.8lx\n", + (unsigned long) insn); + + frame = get_current_frame (); + + /* Is this a sigreturn or rt_sigreturn syscall? Note: these are only useful + for EABI. */ + if (svc_number == 119 || svc_number == 173) + { + if (get_frame_type (frame) == SIGTRAMP_FRAME) + { + CORE_ADDR return_to; + struct symtab_and_line sal; + + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: found " + "sigreturn/rt_sigreturn SVC call. PC in frame = %lx\n", + (unsigned long) get_frame_pc (frame)); + + return_to = frame_unwind_caller_pc (frame); + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: unwind pc = %lx. " + "Setting momentary breakpoint.\n", (unsigned long) return_to); + + gdb_assert (inferior_thread ()->step_resume_breakpoint == NULL); + + sal = find_pc_line (return_to, 0); + sal.pc = return_to; + sal.section = find_pc_overlay (return_to); + sal.explicit_pc = 1; + + frame = get_prev_frame (frame); + + if (frame) + { + inferior_thread ()->step_resume_breakpoint + = set_momentary_breakpoint (gdbarch, sal, get_frame_id (frame), + bp_step_resume); + + /* We need to make sure we actually insert the momentary + breakpoint set above. */ + insert_breakpoints (); + } + else if (debug_displaced) + fprintf_unfiltered (gdb_stderr, "displaced: couldn't find previous " + "frame to set momentary breakpoint for " + "sigreturn/rt_sigreturn\n"); + } + else if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: sigreturn/rt_sigreturn " + "SVC call not in signal trampoline frame\n"); + } + + /* Preparation: If we detect sigreturn, set momentary breakpoint at resume + location, else nothing. + Insn: unmodified svc. + Cleanup: if pc lands in scratch space, pc <- insn_addr + 4 + else leave pc alone. */ + + dsc->modinsn[0] = insn; + + dsc->cleanup = &arm_linux_cleanup_svc; + /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next + instruction. */ + dsc->wrote_to_pc = 1; + + return 0; +} + + +/* The following two functions implement single-stepping over calls to Linux + kernel helper routines, which perform e.g. atomic operations on architecture + variants which don't support them natively. + + When this function is called, the PC will be pointing at the kernel helper + (at an address inaccessible to GDB), and r14 will point to the return + address. Displaced stepping always executes code in the copy area: + so, make the copy-area instruction branch back to the kernel helper (the + "from" address), and make r14 point to the breakpoint in the copy area. In + that way, we regain control once the kernel helper returns, and can clean + up appropriately (as if we had just returned from the kernel helper as it + would have been called from the non-displaced location). */ + +static void +cleanup_kernel_helper_return (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, + struct regcache *regs, + struct displaced_step_closure *dsc) +{ + displaced_write_reg (regs, dsc, ARM_LR_REGNUM, dsc->tmp[0], CANNOT_WRITE_PC); + displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->tmp[0], BRANCH_WRITE_PC); +} + +static void +arm_catch_kernel_helper_return (struct gdbarch *gdbarch, CORE_ADDR from, + CORE_ADDR to, struct regcache *regs, + struct displaced_step_closure *dsc) +{ + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + + dsc->numinsns = 1; + dsc->insn_addr = from; + dsc->cleanup = &cleanup_kernel_helper_return; + /* Say we wrote to the PC, else cleanup will set PC to the next + instruction in the helper, which isn't helpful. */ + dsc->wrote_to_pc = 1; + + /* Preparation: tmp[0] <- r14 + r14 <- +4 + *(+8) <- from + Insn: ldr pc, [r14, #4] + Cleanup: r14 <- tmp[0], pc <- tmp[0]. */ + + dsc->tmp[0] = displaced_read_reg (regs, from, ARM_LR_REGNUM); + displaced_write_reg (regs, dsc, ARM_LR_REGNUM, (ULONGEST) to + 4, + CANNOT_WRITE_PC); + write_memory_unsigned_integer (to + 8, 4, byte_order, from); + + dsc->modinsn[0] = 0xe59ef004; /* ldr pc, [lr, #4]. */ +} + +/* Linux-specific displaced step instruction copying function. Detects when + the program has stepped into a Linux kernel helper routine (which must be + handled as a special case), falling back to arm_displaced_step_copy_insn() + if it hasn't. */ + +static struct displaced_step_closure * +arm_linux_displaced_step_copy_insn (struct gdbarch *gdbarch, + CORE_ADDR from, CORE_ADDR to, + struct regcache *regs) +{ + struct displaced_step_closure *dsc + = xmalloc (sizeof (struct displaced_step_closure)); + + /* Detect when we enter an (inaccessible by GDB) Linux kernel helper, and + stop at the return location. */ + if (from > 0xffff0000) + { + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: detected kernel helper " + "at %.8lx\n", (unsigned long) from); + + arm_catch_kernel_helper_return (gdbarch, from, to, regs, dsc); + } + else + { + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order); + + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx " + "at %.8lx\n", (unsigned long) insn, + (unsigned long) from); + + /* Override the default handling of SVC instructions. */ + dsc->u.svc.copy_svc_os = arm_linux_copy_svc; + + arm_process_displaced_insn (gdbarch, insn, from, to, regs, dsc); + } + + arm_displaced_init_closure (gdbarch, from, to, dsc); + + return dsc; +} + static void arm_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) @@ -657,6 +865,14 @@ arm_linux_init_abi (struct gdbarch_info info, arm_linux_regset_from_core_section); set_gdbarch_get_siginfo_type (gdbarch, linux_get_siginfo_type); + + /* Displaced stepping. */ + set_gdbarch_displaced_step_copy_insn (gdbarch, + arm_linux_displaced_step_copy_insn); + set_gdbarch_displaced_step_fixup (gdbarch, arm_displaced_step_fixup); + set_gdbarch_displaced_step_free_closure (gdbarch, + simple_displaced_step_free_closure); + set_gdbarch_displaced_step_location (gdbarch, displaced_step_at_entry_point); } /* Provide a prototype to silence -Wmissing-prototypes. */ diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 3cc8d01..30b1df6 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -235,6 +235,11 @@ struct arm_prologue_cache struct trad_frame_saved_reg *saved_regs; }; +/* Architecture version for displaced stepping. This effects the behaviour of + certain instructions, and really should not be hard-wired. */ + +#define DISPLACED_STEPPING_ARCH_VERSION 5 + /* Addresses for calling Thumb functions have the bit 0 set. Here are some macros to test, set, or clear bit 0 of addresses. */ #define IS_THUMB_ADDR(addr) ((addr) & 1) @@ -2600,272 +2605,2122 @@ arm_software_single_step (struct frame_info *frame) return 1; } -#include "bfd-in2.h" -#include "libcoff.h" +/* ARM displaced stepping support. -static int -gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) -{ - if (arm_pc_is_thumb (memaddr)) - { - static asymbol *asym; - static combined_entry_type ce; - static struct coff_symbol_struct csym; - static struct bfd fake_bfd; - static bfd_target fake_target; + Generally ARM displaced stepping works as follows: - if (csym.native == NULL) - { - /* Create a fake symbol vector containing a Thumb symbol. - This is solely so that the code in print_insn_little_arm() - and print_insn_big_arm() in opcodes/arm-dis.c will detect - the presence of a Thumb symbol and switch to decoding - Thumb instructions. */ + 1. When an instruction is to be single-stepped, it is first decoded by + arm_process_displaced_insn (called from arm_displaced_step_copy_insn). + Depending on the type of instruction, it is then copied to a scratch + location, possibly in a modified form. The copy_* set of functions + performs such modification, as necessary. A breakpoint is placed after + the modified instruction in the scratch space to return control to GDB. + Note in particular that instructions which modify the PC will no longer + do so after modification. - fake_target.flavour = bfd_target_coff_flavour; - fake_bfd.xvec = &fake_target; - ce.u.syment.n_sclass = C_THUMBEXTFUNC; - csym.native = &ce; - csym.symbol.the_bfd = &fake_bfd; - csym.symbol.name = "fake"; - asym = (asymbol *) & csym; - } + 2. The instruction is single-stepped, by setting the PC to the scratch + location address, and resuming. Control returns to GDB when the + breakpoint is hit. - memaddr = UNMAKE_THUMB_ADDR (memaddr); - info->symbols = &asym; - } - else - info->symbols = NULL; + 3. A cleanup function (cleanup_*) is called corresponding to the copy_* + function used for the current instruction. This function's job is to + put the CPU/memory state back to what it would have been if the + instruction had been executed unmodified in its original location. */ - if (info->endian == BFD_ENDIAN_BIG) - return print_insn_big_arm (memaddr, info); +/* NOP instruction (mov r0, r0). */ +#define ARM_NOP 0xe1a00000 + +/* Helper for register reads for displaced stepping. In particular, this + returns the PC as it would be seen by the instruction at its original + location. */ + +ULONGEST +displaced_read_reg (struct regcache *regs, CORE_ADDR from, int regno) +{ + ULONGEST ret; + + if (regno == 15) + { + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n", + (unsigned long) from + 8); + return (ULONGEST) from + 8; /* Pipeline offset. */ + } else - return print_insn_little_arm (memaddr, info); + { + regcache_cooked_read_unsigned (regs, regno, &ret); + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n", + regno, (unsigned long) ret); + return ret; + } } -/* The following define instruction sequences that will cause ARM - cpu's to take an undefined instruction trap. These are used to - signal a breakpoint to GDB. - - The newer ARMv4T cpu's are capable of operating in ARM or Thumb - modes. A different instruction is required for each mode. The ARM - cpu's can also be big or little endian. Thus four different - instructions are needed to support all cases. - - Note: ARMv4 defines several new instructions that will take the - undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does - not in fact add the new instructions. The new undefined - instructions in ARMv4 are all instructions that had no defined - behaviour in earlier chips. There is no guarantee that they will - raise an exception, but may be treated as NOP's. In practice, it - may only safe to rely on instructions matching: - - 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x - - Even this may only true if the condition predicate is true. The - following use a condition predicate of ALWAYS so it is always TRUE. - - There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, - and NetBSD all use a software interrupt rather than an undefined - instruction to force a trap. This can be handled by by the - abi-specific code during establishment of the gdbarch vector. */ +static int +displaced_in_arm_mode (struct regcache *regs) +{ + ULONGEST ps; -#define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} -#define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} -#define THUMB_LE_BREAKPOINT {0xbe,0xbe} -#define THUMB_BE_BREAKPOINT {0xbe,0xbe} + regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); -static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; -static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; -static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; -static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; + return (ps & CPSR_T) == 0; +} -/* Determine the type and size of breakpoint to insert at PCPTR. Uses - the program counter value to determine whether a 16-bit or 32-bit - breakpoint should be used. It returns a pointer to a string of - bytes that encode a breakpoint instruction, stores the length of - the string to *lenptr, and adjusts the program counter (if - necessary) to point to the actual memory location where the - breakpoint should be inserted. */ +/* Write to the PC as from a branch instruction. */ -static const unsigned char * -arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) +static void +branch_write_pc (struct regcache *regs, ULONGEST val) { - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + if (displaced_in_arm_mode (regs)) + /* Note: If bits 0/1 are set, this branch would be unpredictable for + architecture versions < 6. */ + regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & ~(ULONGEST) 0x3); + else + regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & ~(ULONGEST) 0x1); +} - if (arm_pc_is_thumb (*pcptr)) +/* Write to the PC as from a branch-exchange instruction. */ + +static void +bx_write_pc (struct regcache *regs, ULONGEST val) +{ + ULONGEST ps; + + regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); + + if ((val & 1) == 1) { - *pcptr = UNMAKE_THUMB_ADDR (*pcptr); - *lenptr = tdep->thumb_breakpoint_size; - return tdep->thumb_breakpoint; + regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | CPSR_T); + regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe); + } + else if ((val & 2) == 0) + { + regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, + ps & ~(ULONGEST) CPSR_T); + regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val); } else { - *lenptr = tdep->arm_breakpoint_size; - return tdep->arm_breakpoint; + /* Unpredictable behaviour. Try to do something sensible (switch to ARM + mode, align dest to 4 bytes). */ + warning (_("Single-stepping BX to non-word-aligned ARM instruction.")); + regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, + ps & ~(ULONGEST) CPSR_T); + regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc); } } -/* Extract from an array REGBUF containing the (raw) register state a - function return value of type TYPE, and copy that, in virtual - format, into VALBUF. */ +/* Write to the PC as if from a load instruction. */ static void -arm_extract_return_value (struct type *type, struct regcache *regs, - gdb_byte *valbuf) +load_write_pc (struct regcache *regs, ULONGEST val) { - struct gdbarch *gdbarch = get_regcache_arch (regs); - enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + if (DISPLACED_STEPPING_ARCH_VERSION >= 5) + bx_write_pc (regs, val); + else + branch_write_pc (regs, val); +} - if (TYPE_CODE_FLT == TYPE_CODE (type)) +/* Write to the PC as if from an ALU instruction. */ + +static void +alu_write_pc (struct regcache *regs, ULONGEST val) +{ + if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && displaced_in_arm_mode (regs)) + bx_write_pc (regs, val); + else + branch_write_pc (regs, val); +} + +/* Helper for writing to registers for displaced stepping. Writing to the PC + has a varying effects depending on the instruction which does the write: + this is controlled by the WRITE_PC argument. */ + +void +displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc, + int regno, ULONGEST val, enum pc_write_style write_pc) +{ + if (regno == 15) { - switch (gdbarch_tdep (gdbarch)->fp_model) + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n", + (unsigned long) val); + switch (write_pc) { - case ARM_FLOAT_FPA: - { - /* The value is in register F0 in internal format. We need to - extract the raw value and then convert it to the desired - internal type. */ - bfd_byte tmpbuf[FP_REGISTER_SIZE]; - - regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); - convert_from_extended (floatformat_from_type (type), tmpbuf, - valbuf, gdbarch_byte_order (gdbarch)); - } + case BRANCH_WRITE_PC: + branch_write_pc (regs, val); break; - case ARM_FLOAT_SOFT_FPA: - case ARM_FLOAT_SOFT_VFP: - /* ARM_FLOAT_VFP can arise if this is a variadic function so - not using the VFP ABI code. */ - case ARM_FLOAT_VFP: - regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); - if (TYPE_LENGTH (type) > 4) - regcache_cooked_read (regs, ARM_A1_REGNUM + 1, - valbuf + INT_REGISTER_SIZE); + case BX_WRITE_PC: + bx_write_pc (regs, val); + break; + + case LOAD_WRITE_PC: + load_write_pc (regs, val); + break; + + case ALU_WRITE_PC: + alu_write_pc (regs, val); + break; + + case CANNOT_WRITE_PC: + warning (_("Instruction wrote to PC in an unexpected way when " + "single-stepping")); break; default: - internal_error - (__FILE__, __LINE__, - _("arm_extract_return_value: Floating point model not supported")); - break; + abort (); } - } - else if (TYPE_CODE (type) == TYPE_CODE_INT - || TYPE_CODE (type) == TYPE_CODE_CHAR - || TYPE_CODE (type) == TYPE_CODE_BOOL - || TYPE_CODE (type) == TYPE_CODE_PTR - || TYPE_CODE (type) == TYPE_CODE_REF - || TYPE_CODE (type) == TYPE_CODE_ENUM) - { - /* If the the type is a plain integer, then the access is - straight-forward. Otherwise we have to play around a bit more. */ - int len = TYPE_LENGTH (type); - int regno = ARM_A1_REGNUM; - ULONGEST tmp; - while (len > 0) - { - /* By using store_unsigned_integer we avoid having to do - anything special for small big-endian values. */ - regcache_cooked_read_unsigned (regs, regno++, &tmp); - store_unsigned_integer (valbuf, - (len > INT_REGISTER_SIZE - ? INT_REGISTER_SIZE : len), - byte_order, tmp); - len -= INT_REGISTER_SIZE; - valbuf += INT_REGISTER_SIZE; - } + dsc->wrote_to_pc = 1; } else { - /* For a structure or union the behaviour is as if the value had - been stored to word-aligned memory and then loaded into - registers with 32-bit load instruction(s). */ - int len = TYPE_LENGTH (type); - int regno = ARM_A1_REGNUM; - bfd_byte tmpbuf[INT_REGISTER_SIZE]; - - while (len > 0) - { - regcache_cooked_read (regs, regno++, tmpbuf); - memcpy (valbuf, tmpbuf, - len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); - len -= INT_REGISTER_SIZE; - valbuf += INT_REGISTER_SIZE; - } + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n", + regno, (unsigned long) val); + regcache_cooked_write_unsigned (regs, regno, val); } } - -/* Will a function return an aggregate type in memory or in a - register? Return 0 if an aggregate type can be returned in a - register, 1 if it must be returned in memory. */ +/* This function is used to concisely determine if an instruction INSN + references PC. Register fields of interest in INSN should have the + corresponding fields of BITMASK set to 0b1111. The function returns return 1 + if any of these fields in INSN reference the PC (also 0b1111, r15), else it + returns 0. */ static int -arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) +insn_references_pc (uint32_t insn, uint32_t bitmask) { - int nRc; - enum type_code code; + uint32_t lowbit = 1; - CHECK_TYPEDEF (type); + while (bitmask != 0) + { + uint32_t mask; - /* In the ARM ABI, "integer" like aggregate types are returned in - registers. For an aggregate type to be integer like, its size - must be less than or equal to INT_REGISTER_SIZE and the - offset of each addressable subfield must be zero. Note that bit - fields are not addressable, and all addressable subfields of - unions always start at offset zero. + for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1) + ; - This function is based on the behaviour of GCC 2.95.1. - See: gcc/arm.c: arm_return_in_memory() for details. + if (!lowbit) + break; - Note: All versions of GCC before GCC 2.95.2 do not set up the - parameters correctly for a function returning the following - structure: struct { float f;}; This should be returned in memory, - not a register. Richard Earnshaw sent me a patch, but I do not - know of any way to detect if a function like the above has been - compiled with the correct calling convention. */ + mask = lowbit * 0xf; - /* All aggregate types that won't fit in a register must be returned - in memory. */ - if (TYPE_LENGTH (type) > INT_REGISTER_SIZE) - { - return 1; + if ((insn & mask) == mask) + return 1; + + bitmask &= ~mask; } - /* The AAPCS says all aggregates not larger than a word are returned - in a register. */ - if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) - return 0; + return 0; +} - /* The only aggregate types that can be returned in a register are - structs and unions. Arrays must be returned in memory. */ - code = TYPE_CODE (type); - if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) - { - return 1; - } +/* The simplest copy function. Many instructions have the same effect no + matter what address they are executed at: in those cases, use this. */ - /* Assume all other aggregate types can be returned in a register. - Run a check for structures, unions and arrays. */ - nRc = 0; +static int +copy_unmodified (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, uint32_t insn, + const char *iname, struct displaced_step_closure *dsc) +{ + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, " + "opcode/class '%s' unmodified\n", (unsigned long) insn, + iname); - if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) - { - int i; - /* Need to check if this struct/union is "integer" like. For - this to be true, its size must be less than or equal to - INT_REGISTER_SIZE and the offset of each addressable - subfield must be zero. Note that bit fields are not - addressable, and unions always start at offset zero. If any - of the subfields is a floating point type, the struct/union - cannot be an integer type. */ + dsc->modinsn[0] = insn; - /* For each field in the object, check: + return 0; +} + +/* Preload instructions with immediate offset. */ + +static void +cleanup_preload (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, + struct regcache *regs, struct displaced_step_closure *dsc) +{ + displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); + if (!dsc->u.preload.immed) + displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); +} + +static int +copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, + struct displaced_step_closure *dsc) +{ + unsigned int rn = bits (insn, 16, 19); + ULONGEST rn_val; + CORE_ADDR from = dsc->insn_addr; + + if (!insn_references_pc (insn, 0x000f0000ul)) + return copy_unmodified (gdbarch, insn, "preload", dsc); + + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n", + (unsigned long) insn); + + /* Preload instructions: + + {pli/pld} [rn, #+/-imm] + -> + {pli/pld} [r0, #+/-imm]. */ + + dsc->tmp[0] = displaced_read_reg (regs, from, 0); + rn_val = displaced_read_reg (regs, from, rn); + displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); + + dsc->u.preload.immed = 1; + + dsc->modinsn[0] = insn & 0xfff0ffff; + + dsc->cleanup = &cleanup_preload; + + return 0; +} + +/* Preload instructions with register offset. */ + +static int +copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, + struct displaced_step_closure *dsc) +{ + unsigned int rn = bits (insn, 16, 19); + unsigned int rm = bits (insn, 0, 3); + ULONGEST rn_val, rm_val; + CORE_ADDR from = dsc->insn_addr; + + if (!insn_references_pc (insn, 0x000f000ful)) + return copy_unmodified (gdbarch, insn, "preload reg", dsc); + + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n", + (unsigned long) insn); + + /* Preload register-offset instructions: + + {pli/pld} [rn, rm {, shift}] + -> + {pli/pld} [r0, r1 {, shift}]. */ + + dsc->tmp[0] = displaced_read_reg (regs, from, 0); + dsc->tmp[1] = displaced_read_reg (regs, from, 1); + rn_val = displaced_read_reg (regs, from, rn); + rm_val = displaced_read_reg (regs, from, rm); + displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); + displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC); + + dsc->u.preload.immed = 0; + + dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1; + + dsc->cleanup = &cleanup_preload; + + return 0; +} + +/* Copy/cleanup coprocessor load and store instructions. */ + +static void +cleanup_copro_load_store (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, + struct regcache *regs, + struct displaced_step_closure *dsc) +{ + ULONGEST rn_val = displaced_read_reg (regs, dsc->insn_addr, 0); + + displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); + + if (dsc->u.ldst.writeback) + displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC); +} + +static int +copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn, + struct regcache *regs, + struct displaced_step_closure *dsc) +{ + unsigned int rn = bits (insn, 16, 19); + ULONGEST rn_val; + CORE_ADDR from = dsc->insn_addr; + + if (!insn_references_pc (insn, 0x000f0000ul)) + return copy_unmodified (gdbarch, insn, "copro load/store", dsc); + + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor " + "load/store insn %.8lx\n", (unsigned long) insn); + + /* Coprocessor load/store instructions: + + {stc/stc2} [, #+/-imm] (and other immediate addressing modes) + -> + {stc/stc2} [r0, #+/-imm]. + + ldc/ldc2 are handled identically. */ + + dsc->tmp[0] = displaced_read_reg (regs, from, 0); + rn_val = displaced_read_reg (regs, from, rn); + displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); + + dsc->u.ldst.writeback = bit (insn, 25); + dsc->u.ldst.rn = rn; + + dsc->modinsn[0] = insn & 0xfff0ffff; + + dsc->cleanup = &cleanup_copro_load_store; + + return 0; +} + +/* Clean up branch instructions (actually perform the branch, by setting + PC). */ + +static void +cleanup_branch (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, struct regcache *regs, + struct displaced_step_closure *dsc) +{ + ULONGEST from = dsc->insn_addr; + uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM); + int branch_taken = condition_true (dsc->u.branch.cond, status); + enum pc_write_style write_pc = dsc->u.branch.exchange + ? BX_WRITE_PC : BRANCH_WRITE_PC; + + if (!branch_taken) + return; + + if (dsc->u.branch.link) + { + ULONGEST pc = displaced_read_reg (regs, from, 15); + displaced_write_reg (regs, dsc, 14, pc - 4, CANNOT_WRITE_PC); + } + + displaced_write_reg (regs, dsc, 15, dsc->u.branch.dest, write_pc); +} + +/* Copy B/BL/BLX instructions with immediate destinations. */ + +static int +copy_b_bl_blx (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, uint32_t insn, + struct regcache *regs, struct displaced_step_closure *dsc) +{ + unsigned int cond = bits (insn, 28, 31); + int exchange = (cond == 0xf); + int link = exchange || bit (insn, 24); + CORE_ADDR from = dsc->insn_addr; + long offset; + + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn " + "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b", + (unsigned long) insn); + + /* Implement "BL