From cc91747be98f2a3fc305cf3efc8f3a9b7f6a9f3b Mon Sep 17 00:00:00 2001 From: Shayne Chen Date: Mon, 12 Apr 2021 13:39:54 +0800 Subject: [PATCH] mt76: mt7915: fix rate setting of tx descriptor in testmode Fix ofdm rate index and ldpc setting in rate setting field of tx descriptor. Signed-off-by: Shayne Chen Signed-off-by: Felix Fietkau --- drivers/net/wireless/mediatek/mt76/mt7915/mac.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c index 3f3bfea..f99c269 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c @@ -661,19 +661,18 @@ mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, { #ifdef CONFIG_NL80211_TESTMODE struct mt76_testmode_data *td = &phy->mt76->test; + const struct ieee80211_rate *r; + u8 bw, mode, nss = td->tx_rate_nss; u8 rate_idx = td->tx_rate_idx; - u8 nss = td->tx_rate_nss; - u8 bw, mode; u16 rateval = 0; u32 val; + bool cck = false; + int band; if (skb != phy->mt76->test.tx_skb) return; switch (td->tx_rate_mode) { - case MT76_TM_TX_MODE_CCK: - mode = MT_PHY_TYPE_CCK; - break; case MT76_TM_TX_MODE_HT: nss = 1 + (rate_idx >> 3); mode = MT_PHY_TYPE_HT; @@ -693,7 +692,20 @@ mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, case MT76_TM_TX_MODE_HE_MU: mode = MT_PHY_TYPE_HE_MU; break; + case MT76_TM_TX_MODE_CCK: + cck = true; + fallthrough; case MT76_TM_TX_MODE_OFDM: + band = phy->mt76->chandef.chan->band; + if (band == NL80211_BAND_2GHZ && !cck) + rate_idx += 4; + + r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx]; + val = cck ? r->hw_value_short : r->hw_value; + + mode = val >> 8; + rate_idx = val & 0xff; + break; default: mode = MT_PHY_TYPE_OFDM; break; @@ -748,9 +760,10 @@ mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, if (mode >= MT_PHY_TYPE_HE_SU) val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf); - if (td->tx_rate_ldpc || bw > 0) + if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU)) val |= MT_TXD6_LDPC; + txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID); txwi[6] |= cpu_to_le32(val); txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, phy->test.spe_idx)); -- 2.7.4