From cc723cccabfc74c93bf99458f1a92caff0fc9504 Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Sun, 9 Oct 2016 04:39:13 +0000 Subject: [PATCH] MC: Remove unused entities. llvm-svn: 283691 --- llvm/include/llvm/MC/MCInstrDesc.h | 154 --------------------- llvm/include/llvm/MC/MCMachObjectWriter.h | 8 -- llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h | 10 -- llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h | 3 - llvm/include/llvm/MC/MCStreamer.h | 4 - llvm/include/llvm/MC/MCWin64EH.h | 6 +- llvm/include/llvm/MC/MCWinEH.h | 9 -- llvm/lib/MC/CMakeLists.txt | 1 - llvm/lib/MC/MCAsmStreamer.cpp | 2 +- llvm/lib/MC/MCStreamer.cpp | 4 - llvm/lib/MC/MCWinEH.cpp | 26 ---- .../Target/AArch64/AsmParser/AArch64AsmParser.cpp | 2 +- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 2 +- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +- .../Target/Hexagon/AsmParser/HexagonAsmParser.cpp | 2 +- llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp | 2 +- llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 2 +- llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 2 +- llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp | 2 +- .../Target/SystemZ/AsmParser/SystemZAsmParser.cpp | 2 +- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 2 +- llvm/lib/Target/X86/AsmParser/X86Operand.h | 14 +- .../Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp | 2 +- llvm/utils/TableGen/AsmMatcherEmitter.cpp | 2 +- 24 files changed, 19 insertions(+), 246 deletions(-) delete mode 100644 llvm/lib/MC/MCWinEH.cpp diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h index 340d825..778a864 100644 --- a/llvm/include/llvm/MC/MCInstrDesc.h +++ b/llvm/include/llvm/MC/MCInstrDesc.h @@ -294,80 +294,13 @@ public: /// \brief Return true if this instruction is a comparison. bool isCompare() const { return Flags & (1ULL << MCID::Compare); } - /// \brief Return true if this instruction is a move immediate - /// (including conditional moves) instruction. - bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); } - - /// \brief Return true if this instruction is a bitcast instruction. - bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); } - /// \brief Return true if this is a select instruction. bool isSelect() const { return Flags & (1ULL << MCID::Select); } - /// \brief Return true if this instruction cannot be safely - /// duplicated. For example, if the instruction has a unique labels attached - /// to it, duplicating it would cause multiple definition errors. - bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); } - /// \brief Returns true if the specified instruction has a delay slot which /// must be filled by the code generator. bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); } - /// \brief Return true for instructions that can be folded as memory operands - /// in other instructions. The most common use for this is instructions that - /// are simple loads from memory that don't modify the loaded value in any - /// way, but it can also be used for instructions that can be expressed as - /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be - /// folded when it is beneficial. This should only be set on instructions - /// that return a value in their only virtual register definition. - bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); } - - /// \brief Return true if this instruction behaves - /// the same way as the generic REG_SEQUENCE instructions. - /// E.g., on ARM, - /// dX VMOVDRR rY, rZ - /// is equivalent to - /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. - /// - /// Note that for the optimizers to be able to take advantage of - /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be - /// override accordingly. - bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); } - - /// \brief Return true if this instruction behaves - /// the same way as the generic EXTRACT_SUBREG instructions. - /// E.g., on ARM, - /// rX, rY VMOVRRD dZ - /// is equivalent to two EXTRACT_SUBREG: - /// rX = EXTRACT_SUBREG dZ, ssub_0 - /// rY = EXTRACT_SUBREG dZ, ssub_1 - /// - /// Note that for the optimizers to be able to take advantage of - /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be - /// override accordingly. - bool isExtractSubregLike() const { - return Flags & (1ULL << MCID::ExtractSubreg); - } - - /// \brief Return true if this instruction behaves - /// the same way as the generic INSERT_SUBREG instructions. - /// E.g., on ARM, - /// dX = VSETLNi32 dY, rZ, Imm - /// is equivalent to a INSERT_SUBREG: - /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) - /// - /// Note that for the optimizers to be able to take advantage of - /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be - /// override accordingly. - bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); } - - - /// \brief Return true if this instruction is convergent. - /// - /// Convergent instructions may not be made control-dependent on any - /// additional values. - bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); } - //===--------------------------------------------------------------------===// // Side Effect Analysis //===--------------------------------------------------------------------===// @@ -383,22 +316,6 @@ public: /// may not actually modify anything, for example. bool mayStore() const { return Flags & (1ULL << MCID::MayStore); } - /// \brief Return true if this instruction has side - /// effects that are not modeled by other flags. This does not return true - /// for instructions whose effects are captured by: - /// - /// 1. Their operand list and implicit definition/use list. Register use/def - /// info is explicit for instructions. - /// 2. Memory accesses. Use mayLoad/mayStore. - /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. - /// - /// Examples of side effects would be modifying 'invisible' machine state like - /// a control register, flushing a cache, modifying a register invisible to - /// LLVM, etc. - bool hasUnmodeledSideEffects() const { - return Flags & (1ULL << MCID::UnmodeledSideEffects); - } - //===--------------------------------------------------------------------===// // Flags that indicate whether an instruction can be modified by a method. //===--------------------------------------------------------------------===// @@ -415,36 +332,6 @@ public: /// commute them. bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); } - /// \brief Return true if this is a 2-address instruction which can be changed - /// into a 3-address instruction if needed. Doing this transformation can be - /// profitable in the register allocator, because it means that the - /// instruction can use a 2-address form if possible, but degrade into a less - /// efficient form if the source and dest register cannot be assigned to the - /// same register. For example, this allows the x86 backend to turn a "shl - /// reg, 3" instruction into an LEA instruction, which is the same speed as - /// the shift but has bigger code size. - /// - /// If this returns true, then the target must implement the - /// TargetInstrInfo::convertToThreeAddress method for this instruction, which - /// is allowed to fail if the transformation isn't valid for this specific - /// instruction (e.g. shl reg, 4 on x86). - /// - bool isConvertibleTo3Addr() const { - return Flags & (1ULL << MCID::ConvertibleTo3Addr); - } - - /// \brief Return true if this instruction requires custom insertion support - /// when the DAG scheduler is inserting it into a machine basic block. If - /// this is true for the instruction, it basically means that it is a pseudo - /// instruction used at SelectionDAG time that is expanded out into magic code - /// by the target when MachineInstrs are formed. - /// - /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method - /// is used to insert this into the MachineBasicBlock. - bool usesCustomInsertionHook() const { - return Flags & (1ULL << MCID::UsesCustomInserter); - } - /// \brief Return true if this instruction requires *adjustment* after /// instruction selection by calling a target hook. For example, this can be /// used to fill in ARM 's' optional operand depending on whether the @@ -461,37 +348,6 @@ public: return Flags & (1ULL << MCID::Rematerializable); } - /// \brief Returns true if this instruction has the same cost (or less) than a - /// move instruction. This is useful during certain types of optimizations - /// (e.g., remat during two-address conversion or machine licm) where we would - /// like to remat or hoist the instruction, but not if it costs more than - /// moving the instruction into the appropriate register. Note, we are not - /// marking copies from and to the same register class with this flag. - /// - /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove - /// for different subtargets. - bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); } - - /// \brief Returns true if this instruction source operands have special - /// register allocation requirements that are not captured by the operand - /// register classes. e.g. ARM::STRD's two source registers must be an even / - /// odd pair, ARM::STM registers have to be in ascending order. Post-register - /// allocation passes should not attempt to change allocations for sources of - /// instructions with this flag. - bool hasExtraSrcRegAllocReq() const { - return Flags & (1ULL << MCID::ExtraSrcRegAllocReq); - } - - /// \brief Returns true if this instruction def operands have special register - /// allocation requirements that are not captured by the operand register - /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair, - /// ARM::LDM registers have to be in ascending order. Post-register - /// allocation passes should not attempt to change allocations for definitions - /// of instructions with this flag. - bool hasExtraDefRegAllocReq() const { - return Flags & (1ULL << MCID::ExtraDefRegAllocReq); - } - /// \brief Return a list of registers that are potentially read by any /// instance of this machine instruction. For example, on X86, the "adc" /// instruction adds two register operands and adds the carry bit in from the @@ -535,16 +391,6 @@ public: } /// \brief Return true if this instruction implicitly - /// uses the specified physical register. - bool hasImplicitUseOfPhysReg(unsigned Reg) const { - if (const MCPhysReg *ImpUses = ImplicitUses) - for (; *ImpUses; ++ImpUses) - if (*ImpUses == Reg) - return true; - return false; - } - - /// \brief Return true if this instruction implicitly /// defines the specified physical register. bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI = nullptr) const; diff --git a/llvm/include/llvm/MC/MCMachObjectWriter.h b/llvm/include/llvm/MC/MCMachObjectWriter.h index 1a685db..5e5640e 100644 --- a/llvm/include/llvm/MC/MCMachObjectWriter.h +++ b/llvm/include/llvm/MC/MCMachObjectWriter.h @@ -27,16 +27,11 @@ class MCMachObjectTargetWriter { const unsigned Is64Bit : 1; const uint32_t CPUType; const uint32_t CPUSubtype; - unsigned LocalDifference_RIT; protected: MCMachObjectTargetWriter(bool Is64Bit_, uint32_t CPUType_, uint32_t CPUSubtype_); - void setLocalDifferenceRelocationType(unsigned Type) { - LocalDifference_RIT = Type; - } - public: virtual ~MCMachObjectTargetWriter(); @@ -53,9 +48,6 @@ public: bool is64Bit() const { return Is64Bit; } uint32_t getCPUType() const { return CPUType; } uint32_t getCPUSubtype() const { return CPUSubtype; } - unsigned getLocalDifferenceRelocationType() const { - return LocalDifference_RIT; - } /// @} diff --git a/llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h b/llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h index a90d280..fabae70 100644 --- a/llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h +++ b/llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h @@ -64,21 +64,11 @@ public: /// getStartLoc - Get the location of the first token of this operand. virtual SMLoc getStartLoc() const = 0; - /// getEndLoc - Get the location of the last token of this operand. - virtual SMLoc getEndLoc() const = 0; /// needAddressOf - Do we need to emit code to get the address of the /// variable/label? Only valid when parsing MS-style inline assembly. virtual bool needAddressOf() const { return false; } - /// isOffsetOf - Do we need to emit code to get the offset of the variable, - /// rather then the value of the variable? Only valid when parsing MS-style - /// inline assembly. - virtual bool isOffsetOf() const { return false; } - - /// getOffsetOfLoc - Get the location of the offset operator. - virtual SMLoc getOffsetOfLoc() const { return SMLoc(); } - /// print - Print a debug representation of the operand to the given stream. virtual void print(raw_ostream &OS) const = 0; /// dump - Print to the debug stream. diff --git a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h index b2f7b8e..cab926f 100644 --- a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h +++ b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h @@ -209,9 +209,6 @@ public: return Match_Success; } - virtual void convertToMapAndConstraints(unsigned Kind, - const OperandVector &Operands) = 0; - // Return whether this parser uses assignment statements with equals tokens virtual bool equalIsAsmAssignment() { return true; }; // Return whether this start of statement identifier is a label diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h index 99d07ff..54c0b6b 100644 --- a/llvm/include/llvm/MC/MCStreamer.h +++ b/llvm/include/llvm/MC/MCStreamer.h @@ -199,8 +199,6 @@ protected: return CurrentWinFrameInfo; } - virtual void EmitWindowsUnwindTables(); - virtual void EmitRawTextImpl(StringRef String); public: @@ -277,8 +275,6 @@ public: /// \brief Add explicit comment T. T is required to be a valid /// comment in the output and does not need to be escaped. virtual void addExplicitComment(const Twine &T); - /// \brief Emit added explicit comments. - virtual void emitExplicitComments(); /// AddBlankLine - Emit a blank line to a .s file to pretty it up. virtual void AddBlankLine() {} diff --git a/llvm/include/llvm/MC/MCWin64EH.h b/llvm/include/llvm/MC/MCWin64EH.h index 83ea738..a7e89bb 100644 --- a/llvm/include/llvm/MC/MCWin64EH.h +++ b/llvm/include/llvm/MC/MCWin64EH.h @@ -51,10 +51,10 @@ struct Instruction { } }; -class UnwindEmitter : public WinEH::UnwindEmitter { +class UnwindEmitter { public: - void Emit(MCStreamer &Streamer) const override; - void EmitUnwindInfo(MCStreamer &Streamer, WinEH::FrameInfo *FI) const override; + void Emit(MCStreamer &Streamer) const; + void EmitUnwindInfo(MCStreamer &Streamer, WinEH::FrameInfo *FI) const; }; } } // end namespace llvm diff --git a/llvm/include/llvm/MC/MCWinEH.h b/llvm/include/llvm/MC/MCWinEH.h index 4ca52a6..d7adb81 100644 --- a/llvm/include/llvm/MC/MCWinEH.h +++ b/llvm/include/llvm/MC/MCWinEH.h @@ -52,15 +52,6 @@ struct FrameInfo { : Begin(BeginFuncEHLabel), Function(Function), ChainedParent(ChainedParent) {} }; - -class UnwindEmitter { -public: - virtual ~UnwindEmitter(); - - /// This emits the unwind info sections (.pdata and .xdata in PE/COFF). - virtual void Emit(MCStreamer &Streamer) const = 0; - virtual void EmitUnwindInfo(MCStreamer &Streamer, FrameInfo *FI) const = 0; -}; } } diff --git a/llvm/lib/MC/CMakeLists.txt b/llvm/lib/MC/CMakeLists.txt index 2f1b39e..c207aac 100644 --- a/llvm/lib/MC/CMakeLists.txt +++ b/llvm/lib/MC/CMakeLists.txt @@ -41,7 +41,6 @@ add_llvm_library(LLVMMC MCTargetOptions.cpp MCValue.cpp MCWin64EH.cpp - MCWinEH.cpp MachObjectWriter.cpp StringTableBuilder.cpp SubtargetFeature.cpp diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp index 7b1c59f..a8c37e0 100644 --- a/llvm/lib/MC/MCAsmStreamer.cpp +++ b/llvm/lib/MC/MCAsmStreamer.cpp @@ -117,7 +117,7 @@ public: void emitRawComment(const Twine &T, bool TabPrefix = true) override; void addExplicitComment(const Twine &T) override; - void emitExplicitComments() override; + void emitExplicitComments(); /// AddBlankLine - Emit a blank line to a .s file to pretty it up. void AddBlankLine() override { diff --git a/llvm/lib/MC/MCStreamer.cpp b/llvm/lib/MC/MCStreamer.cpp index 124a191..11c548a 100644 --- a/llvm/lib/MC/MCStreamer.cpp +++ b/llvm/lib/MC/MCStreamer.cpp @@ -72,7 +72,6 @@ raw_ostream &MCStreamer::GetCommentOS() { void MCStreamer::emitRawComment(const Twine &T, bool TabPrefix) {} void MCStreamer::addExplicitComment(const Twine &T) {} -void MCStreamer::emitExplicitComments() {} void MCStreamer::generateCompactUnwindEncodings(MCAsmBackend *MAB) { for (auto &FI : DwarfFrameInfos) @@ -713,9 +712,6 @@ void MCStreamer::EmitRawText(const Twine &T) { EmitRawTextImpl(T.toStringRef(Str)); } -void MCStreamer::EmitWindowsUnwindTables() { -} - void MCStreamer::Finish() { if (!DwarfFrameInfos.empty() && !DwarfFrameInfos.back().End) report_fatal_error("Unfinished frame!"); diff --git a/llvm/lib/MC/MCWinEH.cpp b/llvm/lib/MC/MCWinEH.cpp deleted file mode 100644 index 21a9139..0000000 --- a/llvm/lib/MC/MCWinEH.cpp +++ /dev/null @@ -1,26 +0,0 @@ -//===- lib/MC/MCWinEH.cpp - Windows EH implementation ---------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "llvm/ADT/StringRef.h" -#include "llvm/MC/MCContext.h" -#include "llvm/MC/MCObjectFileInfo.h" -#include "llvm/MC/MCSectionCOFF.h" -#include "llvm/MC/MCStreamer.h" -#include "llvm/MC/MCSymbol.h" -#include "llvm/MC/MCWinEH.h" -#include "llvm/Support/COFF.h" - -namespace llvm { -namespace WinEH { - -UnwindEmitter::~UnwindEmitter() {} - -} -} - diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 130f27d..9ecee0e 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -326,7 +326,7 @@ public: /// getStartLoc - Get the location of the first token of this operand. SMLoc getStartLoc() const override { return StartLoc; } /// getEndLoc - Get the location of the last token of this operand. - SMLoc getEndLoc() const override { return EndLoc; } + SMLoc getEndLoc() const { return EndLoc; } StringRef getToken() const { assert(Kind == k_Token && "Invalid access!"); diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index cab5450..a446de7 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -379,7 +379,7 @@ public: return StartLoc; } - SMLoc getEndLoc() const override { + SMLoc getEndLoc() const { return EndLoc; } diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 2b210ddb..909f939 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -752,7 +752,7 @@ public: /// getStartLoc - Get the location of the first token of this operand. SMLoc getStartLoc() const override { return StartLoc; } /// getEndLoc - Get the location of the last token of this operand. - SMLoc getEndLoc() const override { return EndLoc; } + SMLoc getEndLoc() const { return EndLoc; } /// getLocRange - Get the range between the first and last token of this /// operand. SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index 9ce858f..b97707e 100644 --- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -222,7 +222,7 @@ public: SMLoc getStartLoc() const { return StartLoc; } /// getEndLoc - Get the location of the last token of this operand. - SMLoc getEndLoc() const { return EndLoc; } + SMLoc getEndLoc() { return EndLoc; } unsigned getReg() const { assert(Kind == Register && "Invalid access!"); diff --git a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp index cbb96d8..bad187c 100644 --- a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp +++ b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp @@ -134,7 +134,7 @@ public: SMLoc getStartLoc() const override { return StartLoc; } // getEndLoc - Gets location of the last token of this operand - SMLoc getEndLoc() const override { return EndLoc; } + SMLoc getEndLoc() const { return EndLoc; } unsigned getReg() const override { assert(isReg() && "Invalid type access!"); diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index e4b2a40..890dc2d 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1474,7 +1474,7 @@ public: /// getStartLoc - Get the location of the first token of this operand. SMLoc getStartLoc() const override { return StartLoc; } /// getEndLoc - Get the location of the last token of this operand. - SMLoc getEndLoc() const override { return EndLoc; } + SMLoc getEndLoc() const { return EndLoc; } virtual ~MipsOperand() { switch (Kind) { diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index b55e9c7..8b3eac2 100644 --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -394,7 +394,7 @@ public: SMLoc getStartLoc() const override { return StartLoc; } /// getEndLoc - Get the location of the last token of this operand. - SMLoc getEndLoc() const override { return EndLoc; } + SMLoc getEndLoc() const { return EndLoc; } /// isPPC64 - True if this operand is for an instruction in 64-bit mode. bool isPPC64() const { return IsPPC64; } diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index 288f3c1..4ffb373 100644 --- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -281,7 +281,7 @@ public: return StartLoc; } /// getEndLoc - Get the location of the last token of this operand. - SMLoc getEndLoc() const override { + SMLoc getEndLoc() const { return EndLoc; } diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp index 26a427e..012b82f 100644 --- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp +++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp @@ -261,7 +261,7 @@ public: // Override MCParsedAsmOperand. SMLoc getStartLoc() const override { return StartLoc; } - SMLoc getEndLoc() const override { return EndLoc; } + SMLoc getEndLoc() const { return EndLoc; } void print(raw_ostream &OS) const override; // Used by the TableGen code to add particular types of operand diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index eae22b8..3df2ee7 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -1696,7 +1696,7 @@ std::unique_ptr X86AsmParser::ParseIntelOffsetOfOperator() { unsigned RegNo = is64BitMode() ? X86::RBX : (Parse32 ? X86::EBX : X86::BX); return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true, - OffsetOfLoc, Identifier, Info.OpDecl); + Identifier, Info.OpDecl); } enum IntelOperatorKind { diff --git a/llvm/lib/Target/X86/AsmParser/X86Operand.h b/llvm/lib/Target/X86/AsmParser/X86Operand.h index a04c2f5..6894915 100644 --- a/llvm/lib/Target/X86/AsmParser/X86Operand.h +++ b/llvm/lib/Target/X86/AsmParser/X86Operand.h @@ -31,7 +31,6 @@ struct X86Operand : public MCParsedAsmOperand { } Kind; SMLoc StartLoc, EndLoc; - SMLoc OffsetOfLoc; StringRef SymName; void *OpDecl; bool AddressOf; @@ -75,12 +74,10 @@ struct X86Operand : public MCParsedAsmOperand { /// getStartLoc - Get the location of the first token of this operand. SMLoc getStartLoc() const override { return StartLoc; } /// getEndLoc - Get the location of the last token of this operand. - SMLoc getEndLoc() const override { return EndLoc; } + SMLoc getEndLoc() const { return EndLoc; } /// getLocRange - Get the range between the first and last token of this /// operand. SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } - /// getOffsetOfLoc - Get the location of the offset operator. - SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; } void print(raw_ostream &OS) const override {} @@ -197,10 +194,6 @@ struct X86Operand : public MCParsedAsmOperand { return isImmUnsignedi8Value(CE->getValue()); } - bool isOffsetOf() const override { - return OffsetOfLoc.getPointer(); - } - bool needAddressOf() const override { return AddressOf; } @@ -474,12 +467,11 @@ struct X86Operand : public MCParsedAsmOperand { static std::unique_ptr CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc, - bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(), - StringRef SymName = StringRef(), void *OpDecl = nullptr) { + bool AddressOf = false, StringRef SymName = StringRef(), + void *OpDecl = nullptr) { auto Res = llvm::make_unique(Register, StartLoc, EndLoc); Res->Reg.RegNo = RegNo; Res->AddressOf = AddressOf; - Res->OffsetOfLoc = OffsetOfLoc; Res->SymName = SymName; Res->OpDecl = OpDecl; return Res; diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp index d045118..ea1ed16 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp @@ -22,7 +22,7 @@ public: : MCWinCOFFStreamer(C, AB, *CE, OS) {} void EmitWinEHHandlerData() override; - void EmitWindowsUnwindTables() override; + void EmitWindowsUnwindTables(); void FinishImpl() override; }; diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp index fb71536..0052a6a 100644 --- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp +++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp @@ -2893,7 +2893,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { << " const OperandVector &Operands);\n"; } OS << " void convertToMapAndConstraints(unsigned Kind,\n "; - OS << " const OperandVector &Operands) override;\n"; + OS << " const OperandVector &Operands);\n"; if (HasMnemonicFirst) OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);\n"; OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n" -- 2.7.4