From cc0f619561e3fb81fa89da7b45f4b69296372273 Mon Sep 17 00:00:00 2001 From: Shunzhou Jiang Date: Mon, 15 Oct 2018 10:47:51 +0800 Subject: [PATCH] clk: axg: fix 32bit set mpll clk overflow PD#SWPL-394 Problem: 32bit system clk overflow Solution: let mpll clock not overflow Verify: gxl Change-Id: I90c99c026264bb4d6820cd988bd5f8828456e0f6 Signed-off-by: shunzhou.jiang --- drivers/amlogic/clk/clk-mpll.c | 2 +- drivers/amlogic/clk/gxl/clk_misc.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/amlogic/clk/clk-mpll.c b/drivers/amlogic/clk/clk-mpll.c index 435055b..66bd875 100644 --- a/drivers/amlogic/clk/clk-mpll.c +++ b/drivers/amlogic/clk/clk-mpll.c @@ -28,7 +28,7 @@ #include "clkc.h" /* #undef pr_debug */ /* #define pr_debug pr_info */ -#define SDM_MAX 16384 +#define SDM_MAX 16384ULL #define MAX_RATE 500000000 #define MIN_RATE 5000000 diff --git a/drivers/amlogic/clk/gxl/clk_misc.c b/drivers/amlogic/clk/gxl/clk_misc.c index 774bf09..26e495c 100644 --- a/drivers/amlogic/clk/gxl/clk_misc.c +++ b/drivers/amlogic/clk/gxl/clk_misc.c @@ -100,6 +100,7 @@ static struct clk_divider amclk_div = { .shift = 0, .width = 8, .lock = &clk_lock, + .flags = CLK_DIVIDER_ROUND_CLOSEST, .hw.init = &(struct clk_init_data){ .name = "amclk_div", .ops = &clk_divider_ops, -- 2.7.4