From cbebba4917f104491013cf1434784bd70bbfc1d6 Mon Sep 17 00:00:00 2001 From: Nicolai Haehnle Date: Mon, 23 Apr 2018 13:06:03 +0000 Subject: [PATCH] AMDGPU: Fix SDWA peephole for V_AND_B32 Summary: Found by inspection. We care about the operand that *doesn't* contain the immediate. I believe this is currently not hit because we fold 0xff / 0xffff immediates only later. Change-Id: Ic3cf8538bc7da5eff3200d96eccf9d339e6345a7 Reviewers: arsenm, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45886 llvm-svn: 330586 --- llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp index 648f97a..3da63ac 100644 --- a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp +++ b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp @@ -699,7 +699,7 @@ SIPeepholeSDWA::matchSDWAOperand(MachineInstr &MI) { MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); - if (TRI->isPhysicalRegister(Src1->getReg()) || + if (TRI->isPhysicalRegister(ValSrc->getReg()) || TRI->isPhysicalRegister(Dst->getReg())) break; -- 2.7.4