From cbdee7df06b4a63d01b37842423db24ca117f422 Mon Sep 17 00:00:00 2001 From: "Kazushi (Jam) Marukawa" Date: Wed, 28 Oct 2020 12:51:48 +0900 Subject: [PATCH] [VE] Add vector merger operation instructions Add VMRG/VSHF/VCP/VEX isntructions. Add regression tests too. Also add new patterns to parse new UImm4 oeprand. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D90292 --- llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp | 15 ++++++++++++++ llvm/lib/Target/VE/VEInstrInfo.td | 9 +++++++++ llvm/lib/Target/VE/VEInstrVec.td | 29 ++++++++++++++++++++++++++++ llvm/test/MC/VE/VCP.s | 28 +++++++++++++++++++++++++++ llvm/test/MC/VE/VEX.s | 28 +++++++++++++++++++++++++++ llvm/test/MC/VE/VMRG.s | 24 +++++++++++++++++++++++ llvm/test/MC/VE/VSHF.s | 24 +++++++++++++++++++++++ 7 files changed, 157 insertions(+) create mode 100644 llvm/test/MC/VE/VCP.s create mode 100644 llvm/test/MC/VE/VEX.s create mode 100644 llvm/test/MC/VE/VMRG.s create mode 100644 llvm/test/MC/VE/VSHF.s diff --git a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp index 7eb0394..a64a161 100644 --- a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp +++ b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp @@ -280,6 +280,17 @@ public: } return false; } + bool isUImm4() { + if (!isImm()) + return false; + + // Constant case + if (const auto *ConstExpr = dyn_cast(Imm.Val)) { + int64_t Value = ConstExpr->getValue(); + return isUInt<4>(Value); + } + return false; + } bool isUImm6() { if (!isImm()) return false; @@ -479,6 +490,10 @@ public: addImmOperands(Inst, N); } + void addUImm4Operands(MCInst &Inst, unsigned N) const { + addImmOperands(Inst, N); + } + void addUImm6Operands(MCInst &Inst, unsigned N) const { addImmOperands(Inst, N); } diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td index 2c0678e..df3a447 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.td +++ b/llvm/lib/Target/VE/VEInstrInfo.td @@ -157,6 +157,15 @@ def uimm3 : Operand, PatLeaf<(imm), [{ let ParserMatchClass = UImm3AsmOperand; } +// uimm4 - Generic immediate value. +def UImm4AsmOperand : AsmOperandClass { + let Name = "UImm4"; +} +def uimm4 : Operand, PatLeaf<(imm), [{ + return isUInt<4>(N->getZExtValue()); }], ULO7> { + let ParserMatchClass = UImm4AsmOperand; +} + // uimm6 - Generic immediate value. def UImm6AsmOperand : AsmOperandClass { let Name = "UImm6"; diff --git a/llvm/lib/Target/VE/VEInstrVec.td b/llvm/lib/Target/VE/VEInstrVec.td index d5ca34c..701f9ad 100644 --- a/llvm/lib/Target/VE/VEInstrVec.td +++ b/llvm/lib/Target/VE/VEInstrVec.td @@ -644,6 +644,16 @@ multiclass RVI3mopc, RegisterClass VRC, defm vvi : RVIlm; } +// special RV multiclass with 3 arguments for VSHF. +// e.g. VSHF +let vy = ?, vz = ?, VE_VLIndex = 4 in +multiclass RVSHFmopc, RegisterClass RC, + Operand SIMM = uimm4> { + defm vvr : RVlm; + let cy = 0 in defm vvi : RVlm; +} // Section 8.10.1 - VADD (Vector Add) let cx = 0, cx2 = 0 in @@ -1261,3 +1271,22 @@ let cx = 1 in defm VFIMAS : RVI3m<"vfima.s", 0xef, V64, F32>; // Section 8.15.7 - VFIMS (Vector Floating Iteration Multiply and Subtract) let cx = 0 in defm VFIMSD : RVI3m<"vfims.d", 0xff, V64, I64>; let cx = 1 in defm VFIMSS : RVI3m<"vfims.s", 0xff, V64, F32>; + +//----------------------------------------------------------------------------- +// Section 8.16 - Vector Merger Operation Instructions +//----------------------------------------------------------------------------- + +// Section 8.16.1 - VMRG (Vector Merge) +let cx = 0 in defm VMRG : RVm<"vmrg", 0xd6, V64, I64, VM>; +// FIXME: vmrg.w should be called as pvmrg, but following assembly manual. +let cx = 1 in defm VMRGW : RVm<"vmrg.w", 0xd6, V64, I64, VM512>; +def : MnemonicAlias<"vmrg.l", "vmrg">; + +// Section 8.16.2 - VSHF (Vector Shuffle) +defm VSHF : RVSHFm<"vshf", 0xbc, V64>; + +// Section 8.16.3 - VCP (Vector Compress) +defm VCP : RV1m<"vcp", 0x8d, V64, VM>; + +// Section 8.16.4 - VEX (Vector Expand) +defm VEX : RV1m<"vex", 0x9d, V64, VM>; diff --git a/llvm/test/MC/VE/VCP.s b/llvm/test/MC/VE/VCP.s new file mode 100644 index 0000000..be09207 --- /dev/null +++ b/llvm/test/MC/VE/VCP.s @@ -0,0 +1,28 @@ +# RUN: llvm-mc -triple=ve --show-encoding < %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \ +# RUN: | FileCheck %s --check-prefixes=CHECK-INST + +# CHECK-INST: vcp %v11, %v22 +# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x00,0x00,0x8d] +vcp %v11, %v22 + +# CHECK-INST: vcp %vix, %vix +# CHECK-ENCODING: encoding: [0x00,0xff,0x00,0xff,0x00,0x00,0x00,0x8d] +vcp %vix, %vix + +# CHECK-INST: vcp %vix, %v22 +# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x00,0x00,0x8d] +vcp %vix, %v22 + +# CHECK-INST: vcp %v11, %v22, %vm11 +# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x00,0x0b,0x8d] +vcp %v11, %v22, %vm11 + +# CHECK-INST: vcp %v11, %vix, %vm11 +# CHECK-ENCODING: encoding: [0x00,0xff,0x00,0x0b,0x00,0x00,0x0b,0x8d] +vcp %v11, %vix, %vm11 + +# CHECK-INST: vcp %v12, %v20, %vm12 +# CHECK-ENCODING: encoding: [0x00,0x14,0x00,0x0c,0x00,0x00,0x0c,0x8d] +vcp %v12, %v20, %vm12 diff --git a/llvm/test/MC/VE/VEX.s b/llvm/test/MC/VE/VEX.s new file mode 100644 index 0000000..c0b1681 --- /dev/null +++ b/llvm/test/MC/VE/VEX.s @@ -0,0 +1,28 @@ +# RUN: llvm-mc -triple=ve --show-encoding < %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \ +# RUN: | FileCheck %s --check-prefixes=CHECK-INST + +# CHECK-INST: vex %v11, %v22 +# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x00,0x00,0x9d] +vex %v11, %v22 + +# CHECK-INST: vex %vix, %vix +# CHECK-ENCODING: encoding: [0x00,0xff,0x00,0xff,0x00,0x00,0x00,0x9d] +vex %vix, %vix + +# CHECK-INST: vex %vix, %v22 +# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x00,0x00,0x9d] +vex %vix, %v22 + +# CHECK-INST: vex %v11, %v22, %vm11 +# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x00,0x0b,0x9d] +vex %v11, %v22, %vm11 + +# CHECK-INST: vex %v11, %vix, %vm11 +# CHECK-ENCODING: encoding: [0x00,0xff,0x00,0x0b,0x00,0x00,0x0b,0x9d] +vex %v11, %vix, %vm11 + +# CHECK-INST: vex %v12, %v20, %vm12 +# CHECK-ENCODING: encoding: [0x00,0x14,0x00,0x0c,0x00,0x00,0x0c,0x9d] +vex %v12, %v20, %vm12 diff --git a/llvm/test/MC/VE/VMRG.s b/llvm/test/MC/VE/VMRG.s new file mode 100644 index 0000000..9dd42ae --- /dev/null +++ b/llvm/test/MC/VE/VMRG.s @@ -0,0 +1,24 @@ +# RUN: llvm-mc -triple=ve --show-encoding < %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \ +# RUN: | FileCheck %s --check-prefixes=CHECK-INST + +# CHECK-INST: vmrg %v11, %s20, %v22 +# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x94,0x20,0xd6] +vmrg %v11, %s20, %v22 + +# CHECK-INST: vmrg %vix, %vix, %vix +# CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xd6] +vmrg.l %vix, %vix, %vix + +# CHECK-INST: vmrg.w %vix, -64, %v22 +# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x40,0xa0,0xd6] +vmrg.w %vix, -64, %v22 + +# CHECK-INST: vmrg %v11, 63, %v22, %vm11 +# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x3f,0x2b,0xd6] +vmrg.l %v11, 63, %v22, %vm11 + +# CHECK-INST: vmrg.w %v11, %v23, %v22, %vm12 +# CHECK-ENCODING: encoding: [0x00,0x16,0x17,0x0b,0x00,0x00,0x8c,0xd6] +vmrg.w %v11, %v23, %v22, %vm12 diff --git a/llvm/test/MC/VE/VSHF.s b/llvm/test/MC/VE/VSHF.s new file mode 100644 index 0000000..2047704 --- /dev/null +++ b/llvm/test/MC/VE/VSHF.s @@ -0,0 +1,24 @@ +# RUN: llvm-mc -triple=ve --show-encoding < %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \ +# RUN: | FileCheck %s --check-prefixes=CHECK-INST + +# CHECK-INST: vshf %v11, %v20, %v22, %s20 +# CHECK-ENCODING: encoding: [0x00,0x16,0x14,0x0b,0x00,0x94,0x00,0xbc] +vshf %v11, %v20, %v22, %s20 + +# CHECK-INST: vshf %vix, %vix, %vix, 0 +# CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xbc] +vshf %vix, %vix, %vix, 0 + +# CHECK-INST: vshf %vix, %vix, %v22, 15 +# CHECK-ENCODING: encoding: [0x00,0x16,0xff,0xff,0x00,0x0f,0x00,0xbc] +vshf %vix, %vix, %v22, 15 + +# CHECK-INST: vshf %v11, %vix, %v22, 12 +# CHECK-ENCODING: encoding: [0x00,0x16,0xff,0x0b,0x00,0x0c,0x00,0xbc] +vshf %v11, %vix, %v22, 12 + +# CHECK-INST: vshf %v11, %v23, %v22, %s63 +# CHECK-ENCODING: encoding: [0x00,0x16,0x17,0x0b,0x00,0xbf,0x00,0xbc] +vshf %v11, %v23, %v22, %s63 -- 2.7.4