From cbb588a26486527f71028a3c8e6a979053d7ccd5 Mon Sep 17 00:00:00 2001
From: Robert Lytton <robert@xmos.com>
Date: Mon, 6 Jan 2014 14:20:47 +0000
Subject: [PATCH] XCore target: Optimise entsp / retsp selection

llvm-svn: 198612
---
 llvm/lib/Target/XCore/XCoreFrameLowering.cpp | 10 +++++++++-
 llvm/test/CodeGen/XCore/epilogue_prologue.ll | 14 ++++++++------
 llvm/test/CodeGen/XCore/scavenging.ll        |  5 ++---
 3 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp
index 22d0e66..3d1fb9c 100644
--- a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp
@@ -427,12 +427,20 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
                                      RegScavenger *RS) const {
   XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
 
+  bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
+  // If we need to extend the stack it is more efficient to use entsp / retsp.
+  // We force the LR to be saved so these instructions are used.
+  if (!LRUsed && !MF.getFunction()->isVarArg() &&
+      MF.getFrameInfo()->estimateStackSize(MF))
+    LRUsed = true;
+
   // We will handling LR in the prologue/epilogue
   // and space on the stack ourselves.
-  if (MF.getRegInfo().isPhysRegUsed(XCore::LR)) {
+  if (LRUsed) {
     MF.getRegInfo().setPhysRegUnused(XCore::LR);
     XFI->createLRSpillSlot(MF);
   }
+
   // A callee save register is used to hold the FP.
   // This needs saving / restoring in the epilogue / prologue.
   if (hasFP(MF))
diff --git a/llvm/test/CodeGen/XCore/epilogue_prologue.ll b/llvm/test/CodeGen/XCore/epilogue_prologue.ll
index 2898ae5..14f04a3 100644
--- a/llvm/test/CodeGen/XCore/epilogue_prologue.ll
+++ b/llvm/test/CodeGen/XCore/epilogue_prologue.ll
@@ -61,9 +61,11 @@ entry:
 
 ; FP + large frame: spill FP+SR = entsp 2 + 100000
 ; CHECKFP-LABEL: f4
-; CHECKFP: extsp 65535
+; CHECKFP: entsp 65535
 ; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_def_cfa_offset 262140
+; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .cfi_offset 15, 0
 ; CHECKFP-NEXT: extsp 34467
 ; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
 ; CHECKFP-NEXT: .cfi_def_cfa_offset 400008
@@ -76,20 +78,20 @@ entry:
 ; CHECKFP-NEXT: set sp, r10
 ; CHECKFP-NEXT: ldw r10, sp[1]
 ; CHECKFP-NEXT: ldaw sp, sp[65535]
-; CHECKFP-NEXT: ldaw sp, sp[34467]
-; CHECKFP-NEXT: retsp 0
+; CHECKFP-NEXT: retsp 34467
 ;
 ; !FP + large frame: spill SR+SR = entsp 2 + 100000
 ; CHECK-LABEL: f4
-; CHECK: extsp 65535
+; CHECK: entsp 65535
 ; CHECK-NEXT: .Ltmp{{[0-9]+}}
 ; CHECK-NEXT: .cfi_def_cfa_offset 262140
+; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .cfi_offset 15, 0
 ; CHECK-NEXT: extsp 34467
 ; CHECK-NEXT: .Ltmp{{[0-9]+}}
 ; CHECK-NEXT: .cfi_def_cfa_offset 400008
 ; CHECK-NEXT: ldaw sp, sp[65535]
-; CHECK-NEXT: ldaw sp, sp[34467]
-; CHECK-NEXT: retsp 0
+; CHECK-NEXT: retsp 34467
 define void @f4() {
 entry:
   %0 = alloca [100000 x i32]
diff --git a/llvm/test/CodeGen/XCore/scavenging.ll b/llvm/test/CodeGen/XCore/scavenging.ll
index f96ecd3..a0c8a2e 100644
--- a/llvm/test/CodeGen/XCore/scavenging.ll
+++ b/llvm/test/CodeGen/XCore/scavenging.ll
@@ -69,7 +69,7 @@ declare void @g(i32*, i32*)
 ; CHECK: .text
 ; !FP + large frame: spill SR+SR = entsp 2 + 100000
 ; CHECK-LABEL: ScavengeSlots:
-; CHECK: extsp 65535
+; CHECK: entsp 65535
 ; CHECK: extsp 34467
 ; scavenge r11
 ; CHECK: ldaw r11, sp[0]
@@ -97,10 +97,9 @@ declare void @g(i32*, i32*)
 ; CHECK: ldw r1, cp{{\[}}[[INDEX4]]{{\]}}
 ; CHECK: stw r11, r0[r1]
 ; CHECK: ldaw sp, sp[65535]
-; CHECK: ldaw sp, sp[34467]
 ; CHECK: ldw r4, sp[1]
 ; CHECK: ldw r5, sp[0]
-; CHECK: retsp 0
+; CHECK: retsp 34467
 define void @ScavengeSlots(i32 %r0, i32 %r1, i32 %r2, i32 %r3, i32 %r4) nounwind {
 entry:
   %Data = alloca [100000 x i32]
-- 
2.7.4