From cba0c6d0c9d2c610c566e4b46b8f0315a2cfebbc Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 4 Feb 2019 22:26:21 +0000 Subject: [PATCH] AMDGPU: Don't rematerialize mov with implicit operands This was pulling the mov used for register indexing on gfx9 out of the loop. llvm-svn: 353101 --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 3 +- llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir | 112 +++++++++++++++++++++ 2 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index b857d9d..06c080c 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -140,7 +140,8 @@ bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI, case AMDGPU::V_MOV_B32_e32: case AMDGPU::V_MOV_B32_e64: case AMDGPU::V_MOV_B64_PSEUDO: - return true; + // No implicit operands. + return MI.getNumOperands() == MI.getDesc().getNumOperands(); default: return false; } diff --git a/llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir b/llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir new file mode 100644 index 0000000..8d7a93e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir @@ -0,0 +1,112 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-after=phi-node-elimination -stop-before=greedy -o - %s | FileCheck -check-prefix=GFX9 %s + +# Make sure that the V_MOV_B32 isn't rematerialized out of the loop. This was also breaking RenameIndependentSubregisters which missed the use of all subregisters. + +--- +name: index_vgpr_waterfall_loop +tracksRegLiveness: true +liveins: + - { reg: '$vgpr0', virtual-reg: '%0' } + - { reg: '$vgpr1', virtual-reg: '%1' } + - { reg: '$vgpr2', virtual-reg: '%2' } + - { reg: '$vgpr3', virtual-reg: '%3' } + - { reg: '$vgpr4', virtual-reg: '%4' } + - { reg: '$vgpr5', virtual-reg: '%5' } + - { reg: '$vgpr6', virtual-reg: '%6' } + - { reg: '$vgpr7', virtual-reg: '%7' } + - { reg: '$vgpr8', virtual-reg: '%8' } + - { reg: '$vgpr9', virtual-reg: '%9' } + - { reg: '$vgpr10', virtual-reg: '%10' } + - { reg: '$vgpr11', virtual-reg: '%11' } + - { reg: '$vgpr12', virtual-reg: '%12' } + - { reg: '$vgpr13', virtual-reg: '%13' } + - { reg: '$vgpr14', virtual-reg: '%14' } + - { reg: '$vgpr15', virtual-reg: '%15' } + - { reg: '$vgpr16', virtual-reg: '%16' } + - { reg: '$sgpr30_sgpr31', virtual-reg: '%17' } +body: | + ; GFX9-LABEL: name: index_vgpr_waterfall_loop + ; GFX9: bb.0: + ; GFX9: successors: %bb.1(0x80000000) + ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $sgpr30_sgpr31 + ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31 + ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr16 + ; GFX9: undef %18.sub15:vreg_512 = COPY $vgpr15 + ; GFX9: %18.sub14:vreg_512 = COPY $vgpr14 + ; GFX9: %18.sub13:vreg_512 = COPY $vgpr13 + ; GFX9: %18.sub12:vreg_512 = COPY $vgpr12 + ; GFX9: %18.sub11:vreg_512 = COPY $vgpr11 + ; GFX9: %18.sub10:vreg_512 = COPY $vgpr10 + ; GFX9: %18.sub9:vreg_512 = COPY $vgpr9 + ; GFX9: %18.sub8:vreg_512 = COPY $vgpr8 + ; GFX9: %18.sub7:vreg_512 = COPY $vgpr7 + ; GFX9: %18.sub6:vreg_512 = COPY $vgpr6 + ; GFX9: %18.sub5:vreg_512 = COPY $vgpr5 + ; GFX9: %18.sub4:vreg_512 = COPY $vgpr4 + ; GFX9: %18.sub3:vreg_512 = COPY $vgpr3 + ; GFX9: %18.sub2:vreg_512 = COPY $vgpr2 + ; GFX9: %18.sub1:vreg_512 = COPY $vgpr1 + ; GFX9: %18.sub0:vreg_512 = COPY $vgpr0 + ; GFX9: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 15, [[COPY1]], implicit $exec + ; GFX9: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GFX9: bb.1: + ; GFX9: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; GFX9: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[V_AND_B32_e32_]], implicit $exec + ; GFX9: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]], [[V_AND_B32_e32_]], implicit $exec + ; GFX9: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX9: S_SET_GPR_IDX_ON [[V_READFIRSTLANE_B32_]], 1, implicit-def $m0, implicit undef $m0 + ; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef %18.sub0, implicit $exec, implicit %18, implicit $m0 + ; GFX9: S_SET_GPR_IDX_OFF + ; GFX9: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def dead $scc + ; GFX9: S_CBRANCH_EXECNZ %bb.1, implicit $exec + ; GFX9: bb.2: + ; GFX9: $exec = S_MOV_B64 [[S_MOV_B64_]] + ; GFX9: $sgpr30_sgpr31 = COPY [[COPY]] + ; GFX9: $vgpr0 = COPY [[V_MOV_B32_e32_]] + ; GFX9: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit undef $vgpr1, implicit undef $vgpr2, implicit undef $vgpr3 + bb.0: + successors: %bb.1 + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $sgpr30_sgpr31 + + %17:sreg_64 = COPY killed $sgpr30_sgpr31 + %16:vgpr_32 = COPY killed $vgpr16 + %15:vgpr_32 = COPY killed $vgpr15 + %14:vgpr_32 = COPY killed $vgpr14 + %13:vgpr_32 = COPY killed $vgpr13 + %12:vgpr_32 = COPY killed $vgpr12 + %11:vgpr_32 = COPY killed $vgpr11 + %10:vgpr_32 = COPY killed $vgpr10 + %9:vgpr_32 = COPY killed $vgpr9 + %8:vgpr_32 = COPY killed $vgpr8 + %7:vgpr_32 = COPY killed $vgpr7 + %6:vgpr_32 = COPY killed $vgpr6 + %5:vgpr_32 = COPY killed $vgpr5 + %4:vgpr_32 = COPY killed $vgpr4 + %3:vgpr_32 = COPY killed $vgpr3 + %2:vgpr_32 = COPY killed $vgpr2 + %1:vgpr_32 = COPY killed $vgpr1 + %0:vgpr_32 = COPY killed $vgpr0 + %18:vreg_512 = REG_SEQUENCE killed %0, %subreg.sub0, killed %1, %subreg.sub1, killed %2, %subreg.sub2, killed %3, %subreg.sub3, killed %4, %subreg.sub4, killed %5, %subreg.sub5, killed %6, %subreg.sub6, killed %7, %subreg.sub7, killed %8, %subreg.sub8, killed %9, %subreg.sub9, killed %10, %subreg.sub10, killed %11, %subreg.sub11, killed %12, %subreg.sub12, killed %13, %subreg.sub13, killed %14, %subreg.sub14, killed %15, %subreg.sub15 + %19:vgpr_32 = V_AND_B32_e32 15, killed %16, implicit $exec + %20:sreg_64_xexec = S_MOV_B64 $exec + + bb.1: + successors: %bb.1, %bb.2 + + %21:sgpr_32 = V_READFIRSTLANE_B32 %19, implicit $exec + %22:sreg_64 = V_CMP_EQ_U32_e64 %21, %19, implicit $exec + %23:sreg_64 = S_AND_SAVEEXEC_B64 killed %22, implicit-def $exec, implicit-def dead $scc, implicit $exec + S_SET_GPR_IDX_ON killed %21, 1, implicit-def $m0, implicit undef $m0 + %24:vgpr_32 = V_MOV_B32_e32 undef %18.sub0, implicit $exec, implicit %18, implicit $m0 + S_SET_GPR_IDX_OFF + $exec = S_XOR_B64_term $exec, killed %23, implicit-def dead $scc + S_CBRANCH_EXECNZ %bb.1, implicit $exec + + bb.2: + $exec = S_MOV_B64 killed %20 + $sgpr30_sgpr31 = COPY killed %17 + $vgpr0 = COPY killed %24 + S_SETPC_B64_return killed $sgpr30_sgpr31, implicit killed $vgpr0, implicit undef $vgpr1, implicit undef $vgpr2, implicit undef $vgpr3 + +... -- 2.7.4