From cb8b40b08d38bb4ce4b78547cd91b67d9e042abd Mon Sep 17 00:00:00 2001 From: Jack Carter Date: Thu, 26 Sep 2013 21:31:43 +0000 Subject: [PATCH] [mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461 --- llvm/lib/Target/Mips/MipsMSAInstrFormats.td | 7 + llvm/lib/Target/Mips/MipsMSAInstrInfo.td | 229 ++++++++++++------------- llvm/test/MC/Mips/msa/test_3rf.s | 252 ++++++++++++++++++++++++++++ 3 files changed, 376 insertions(+), 112 deletions(-) create mode 100644 llvm/test/MC/Mips/msa/test_3rf.s diff --git a/llvm/lib/Target/Mips/MipsMSAInstrFormats.td b/llvm/lib/Target/Mips/MipsMSAInstrFormats.td index ddd3110..5667890 100644 --- a/llvm/lib/Target/Mips/MipsMSAInstrFormats.td +++ b/llvm/lib/Target/Mips/MipsMSAInstrFormats.td @@ -76,8 +76,15 @@ class MSA_3R_FMT major, bits<2> df, bits<6> minor>: MSAInst { } class MSA_3RF_FMT major, bits<1> df, bits<6> minor>: MSAInst { + bits<5> wt; + bits<5> ws; + bits<5> wd; + let Inst{25-22} = major; let Inst{21} = df; + let Inst{20-16} = wt; + let Inst{15-11} = ws; + let Inst{10-6} = wd; let Inst{5-0} = minor; } diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td index af0e5e4..76fcdcc 100644 --- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td @@ -1175,28 +1175,16 @@ class MSA_3R_4R_DESC_BASE { - dag OutOperandList = (outs RCWD:$wd); - dag InOperandList = (ins RCWS:$ws, RCWT:$wt); - string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); - list Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, RCWT:$wt))]; - InstrItinClass Itinerary = itin; -} + RegisterOperand ROWD, RegisterOperand ROWS = ROWD, + RegisterOperand ROWT = ROWD, + InstrItinClass itin = NoItinerary> : + MSA_3R_DESC_BASE; class MSA_3RF_4RF_DESC_BASE { - dag OutOperandList = (outs RCWD:$wd); - dag InOperandList = (ins RCWD:$wd_in, RCWS:$ws, RCWT:$wt); - string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); - list Pattern = [(set RCWD:$wd, - (OpNode RCWD:$wd_in, RCWS:$ws, RCWT:$wt))]; - InstrItinClass Itinerary = itin; - string Constraints = "$wd = $wd_in"; -} + RegisterOperand ROWD, RegisterOperand ROWS = ROWD, + RegisterOperand ROWT = ROWD, + InstrItinClass itin = NoItinerary> : + MSA_3R_4R_DESC_BASE; class MSA_CBRANCH_DESC_BASE { dag OutOperandList = (outs); @@ -1635,17 +1623,19 @@ class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; -class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128W>, IsCommutable; -class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128D>, IsCommutable; +class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>, + IsCommutable; +class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>, + IsCommutable; -class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128W>, +class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>, IsCommutable; -class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128D>, +class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>, IsCommutable; -class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128W>, +class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>, IsCommutable; -class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128D>, +class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>, IsCommutable; class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w, @@ -1653,57 +1643,59 @@ class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w, class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d, MSA128DOpnd>; -class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128W>; -class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128D>; +class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>; +class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>; -class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128W>; -class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128D>; +class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>; +class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>; -class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128W>, +class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>, IsCommutable; -class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128D>, +class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>, IsCommutable; -class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128W>, +class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>, IsCommutable; -class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128D>, +class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>, IsCommutable; -class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128W>, +class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>, IsCommutable; -class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128D>, +class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>, IsCommutable; -class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128W>, +class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>, IsCommutable; -class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128D>, +class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>, IsCommutable; -class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128W>, +class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>, IsCommutable; -class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128D>, +class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>, IsCommutable; -class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128W>, +class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>, IsCommutable; -class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128D>, +class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>, IsCommutable; -class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128W>, +class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>, IsCommutable; -class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128D>, +class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>, IsCommutable; -class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128W>; -class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128D>; +class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>; +class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>; class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h, - MSA128H, MSA128W, MSA128W>; + MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, - MSA128W, MSA128D, MSA128D>; + MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; -class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", int_mips_fexp2_w, MSA128W>; -class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", int_mips_fexp2_d, MSA128D>; +class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", int_mips_fexp2_w, + MSA128WOpnd>; +class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", int_mips_fexp2_d, + MSA128DOpnd>; class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, MSA128WOpnd, MSA128HOpnd>; @@ -1746,33 +1738,33 @@ class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", int_mips_fmadd_w, - MSA128W>; + MSA128WOpnd>; class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", int_mips_fmadd_d, - MSA128D>; + MSA128DOpnd>; -class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128W>; -class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128D>; +class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>; +class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>; class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w, - MSA128W>; + MSA128WOpnd>; class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d, - MSA128D>; + MSA128DOpnd>; -class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128W>; -class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128D>; +class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>; +class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>; class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w, - MSA128W>; + MSA128WOpnd>; class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d, - MSA128D>; + MSA128DOpnd>; class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", int_mips_fmsub_w, - MSA128W>; + MSA128WOpnd>; class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", int_mips_fmsub_d, - MSA128D>; + MSA128DOpnd>; -class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128W>; -class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128D>; +class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>; +class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>; class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>; class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>; @@ -1785,44 +1777,54 @@ class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w, class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d, MSA128DOpnd>; -class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128W>; -class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128D>; +class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>; +class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>; -class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128W>; -class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128D>; +class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>; +class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>; -class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128W>; -class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128D>; +class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>; +class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>; -class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128W>; -class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128D>; +class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>; +class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>; -class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128W>; -class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128D>; +class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>; +class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>; -class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128W>; -class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128D>; +class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>; +class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>; class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>; class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>; -class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128W>; -class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128D>; +class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>; +class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>; -class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w, MSA128W>; -class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d, MSA128D>; +class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w, + MSA128WOpnd>; +class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d, + MSA128DOpnd>; -class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w, MSA128W>; -class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d, MSA128D>; +class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w, + MSA128WOpnd>; +class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d, + MSA128DOpnd>; -class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w, MSA128W>; -class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d, MSA128D>; +class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w, + MSA128WOpnd>; +class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d, + MSA128DOpnd>; -class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w, MSA128W>; -class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d, MSA128D>; +class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w, + MSA128WOpnd>; +class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d, + MSA128DOpnd>; -class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, MSA128W>; -class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, MSA128D>; +class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, + MSA128WOpnd>; +class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, + MSA128DOpnd>; class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", int_mips_ftrunc_s_w, MSA128WOpnd>; @@ -1845,9 +1847,9 @@ class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d, MSA128DOpnd>; class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h, - MSA128H, MSA128W, MSA128W>; + MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w, - MSA128W, MSA128D, MSA128D>; + MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; @@ -1947,14 +1949,14 @@ class LDX_W_DESC : LDX_DESC_BASE<"ldx.w", load, v4i32, MSA128W>; class LDX_D_DESC : LDX_DESC_BASE<"ldx.d", load, v2i64, MSA128D>; class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, - MSA128H>; + MSA128HOpnd>; class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w, - MSA128W>; + MSA128WOpnd>; class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h, - MSA128H>; + MSA128HOpnd>; class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w, - MSA128W>; + MSA128WOpnd>; class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", int_mips_maddv_b, MSA128BOpnd>; @@ -2050,14 +2052,14 @@ class MOVE_V_DESC { } class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h, - MSA128H>; + MSA128HOpnd>; class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w, - MSA128W>; + MSA128WOpnd>; class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h, - MSA128H>; + MSA128HOpnd>; class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w, - MSA128W>; + MSA128WOpnd>; class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", int_mips_msubv_b, MSA128BOpnd>; @@ -2068,13 +2070,15 @@ class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", int_mips_msubv_w, class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", int_mips_msubv_d, MSA128DOpnd>; -class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h, MSA128H>; -class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w, MSA128W>; +class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h, + MSA128HOpnd>; +class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w, + MSA128WOpnd>; class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h, - MSA128H>; + MSA128HOpnd>; class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w, - MSA128W>; + MSA128WOpnd>; class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>; class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>; @@ -3121,19 +3125,20 @@ def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrRegImm:$addr), def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrRegImm:$addr), (ST_D MSA128D:$ws, addrRegImm:$addr)>; -class MSA_FABS_PSEUDO_DESC_BASE : - MipsPseudo<(outs RCWD:$wd), - (ins RCWS:$ws), - [(set RCWD:$wd, (fabs RCWS:$ws))]> { + MipsPseudo<(outs ROWD:$wd), + (ins ROWS:$ws), + [(set ROWD:$wd, (fabs ROWS:$ws))]> { InstrItinClass Itinerary = itin; } -def FABS_W : MSA_FABS_PSEUDO_DESC_BASE, - PseudoInstExpansion<(FMAX_A_W MSA128W:$wd, MSA128W:$ws, - MSA128W:$ws)>; -def FABS_D : MSA_FABS_PSEUDO_DESC_BASE, - PseudoInstExpansion<(FMAX_A_D MSA128D:$wd, MSA128D:$ws, - MSA128D:$ws)>; +def FABS_W : MSA_FABS_PSEUDO_DESC_BASE, + PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, + MSA128WOpnd:$ws)>; +def FABS_D : MSA_FABS_PSEUDO_DESC_BASE, + PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, + MSA128DOpnd:$ws)>; class MSABitconvertPat preds = [HasMSA]> : diff --git a/llvm/test/MC/Mips/msa/test_3rf.s b/llvm/test/MC/Mips/msa/test_3rf.s new file mode 100644 index 0000000..f45557e --- /dev/null +++ b/llvm/test/MC/Mips/msa/test_3rf.s @@ -0,0 +1,252 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 -mattr=+msa -arch=mips | FileCheck %s +# +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa -arch=mips -filetype=obj -o - | llvm-objdump -d -triple=mipsel-unknown-linux -mattr=+msa -arch=mips - | FileCheck %s -check-prefix=CHECKOBJDUMP +# +# CHECK: fadd.w $w28, $w19, $w28 # encoding: [0x78,0x1c,0x9f,0x1b] +# CHECK: fadd.d $w13, $w2, $w29 # encoding: [0x78,0x3d,0x13,0x5b] +# CHECK: fcaf.w $w14, $w11, $w25 # encoding: [0x78,0x19,0x5b,0x9a] +# CHECK: fcaf.d $w1, $w1, $w19 # encoding: [0x78,0x33,0x08,0x5a] +# CHECK: fceq.w $w1, $w23, $w16 # encoding: [0x78,0x90,0xb8,0x5a] +# CHECK: fceq.d $w0, $w8, $w16 # encoding: [0x78,0xb0,0x40,0x1a] +# CHECK: fcle.w $w16, $w9, $w24 # encoding: [0x79,0x98,0x4c,0x1a] +# CHECK: fcle.d $w27, $w14, $w1 # encoding: [0x79,0xa1,0x76,0xda] +# CHECK: fclt.w $w28, $w8, $w8 # encoding: [0x79,0x08,0x47,0x1a] +# CHECK: fclt.d $w30, $w25, $w11 # encoding: [0x79,0x2b,0xcf,0x9a] +# CHECK: fcne.w $w2, $w18, $w23 # encoding: [0x78,0xd7,0x90,0x9c] +# CHECK: fcne.d $w14, $w20, $w15 # encoding: [0x78,0xef,0xa3,0x9c] +# CHECK: fcor.w $w10, $w18, $w25 # encoding: [0x78,0x59,0x92,0x9c] +# CHECK: fcor.d $w17, $w25, $w11 # encoding: [0x78,0x6b,0xcc,0x5c] +# CHECK: fcueq.w $w14, $w2, $w21 # encoding: [0x78,0xd5,0x13,0x9a] +# CHECK: fcueq.d $w29, $w3, $w7 # encoding: [0x78,0xe7,0x1f,0x5a] +# CHECK: fcule.w $w17, $w5, $w3 # encoding: [0x79,0xc3,0x2c,0x5a] +# CHECK: fcule.d $w31, $w1, $w30 # encoding: [0x79,0xfe,0x0f,0xda] +# CHECK: fcult.w $w6, $w25, $w9 # encoding: [0x79,0x49,0xc9,0x9a] +# CHECK: fcult.d $w27, $w8, $w17 # encoding: [0x79,0x71,0x46,0xda] +# CHECK: fcun.w $w4, $w20, $w8 # encoding: [0x78,0x48,0xa1,0x1a] +# CHECK: fcun.d $w29, $w11, $w3 # encoding: [0x78,0x63,0x5f,0x5a] +# CHECK: fcune.w $w13, $w18, $w19 # encoding: [0x78,0x93,0x93,0x5c] +# CHECK: fcune.d $w16, $w26, $w21 # encoding: [0x78,0xb5,0xd4,0x1c] +# CHECK: fdiv.w $w13, $w24, $w2 # encoding: [0x78,0xc2,0xc3,0x5b] +# CHECK: fdiv.d $w19, $w4, $w25 # encoding: [0x78,0xf9,0x24,0xdb] +# CHECK: fexdo.h $w8, $w0, $w16 # encoding: [0x7a,0x10,0x02,0x1b] +# CHECK: fexdo.w $w0, $w13, $w27 # encoding: [0x7a,0x3b,0x68,0x1b] +# CHECK: fexp2.w $w17, $w0, $w3 # encoding: [0x79,0xc3,0x04,0x5b] +# CHECK: fexp2.d $w22, $w0, $w10 # encoding: [0x79,0xea,0x05,0x9b] +# CHECK: fmadd.w $w29, $w6, $w23 # encoding: [0x79,0x17,0x37,0x5b] +# CHECK: fmadd.d $w11, $w28, $w21 # encoding: [0x79,0x35,0xe2,0xdb] +# CHECK: fmax.w $w0, $w23, $w13 # encoding: [0x7b,0x8d,0xb8,0x1b] +# CHECK: fmax.d $w26, $w18, $w8 # encoding: [0x7b,0xa8,0x96,0x9b] +# CHECK: fmax_a.w $w10, $w16, $w10 # encoding: [0x7b,0xca,0x82,0x9b] +# CHECK: fmax_a.d $w30, $w9, $w22 # encoding: [0x7b,0xf6,0x4f,0x9b] +# CHECK: fmin.w $w24, $w1, $w30 # encoding: [0x7b,0x1e,0x0e,0x1b] +# CHECK: fmin.d $w27, $w27, $w10 # encoding: [0x7b,0x2a,0xde,0xdb] +# CHECK: fmin_a.w $w10, $w29, $w20 # encoding: [0x7b,0x54,0xea,0x9b] +# CHECK: fmin_a.d $w13, $w30, $w24 # encoding: [0x7b,0x78,0xf3,0x5b] +# CHECK: fmsub.w $w17, $w25, $w0 # encoding: [0x79,0x40,0xcc,0x5b] +# CHECK: fmsub.d $w8, $w18, $w16 # encoding: [0x79,0x70,0x92,0x1b] +# CHECK: fmul.w $w3, $w15, $w15 # encoding: [0x78,0x8f,0x78,0xdb] +# CHECK: fmul.d $w9, $w30, $w10 # encoding: [0x78,0xaa,0xf2,0x5b] +# CHECK: fsaf.w $w25, $w5, $w10 # encoding: [0x7a,0x0a,0x2e,0x5a] +# CHECK: fsaf.d $w25, $w3, $w29 # encoding: [0x7a,0x3d,0x1e,0x5a] +# CHECK: fseq.w $w11, $w17, $w13 # encoding: [0x7a,0x8d,0x8a,0xda] +# CHECK: fseq.d $w29, $w0, $w31 # encoding: [0x7a,0xbf,0x07,0x5a] +# CHECK: fsle.w $w30, $w31, $w31 # encoding: [0x7b,0x9f,0xff,0x9a] +# CHECK: fsle.d $w18, $w23, $w24 # encoding: [0x7b,0xb8,0xbc,0x9a] +# CHECK: fslt.w $w12, $w5, $w6 # encoding: [0x7b,0x06,0x2b,0x1a] +# CHECK: fslt.d $w16, $w26, $w21 # encoding: [0x7b,0x35,0xd4,0x1a] +# CHECK: fsne.w $w30, $w1, $w12 # encoding: [0x7a,0xcc,0x0f,0x9c] +# CHECK: fsne.d $w14, $w13, $w23 # encoding: [0x7a,0xf7,0x6b,0x9c] +# CHECK: fsor.w $w27, $w13, $w27 # encoding: [0x7a,0x5b,0x6e,0xdc] +# CHECK: fsor.d $w12, $w24, $w11 # encoding: [0x7a,0x6b,0xc3,0x1c] +# CHECK: fsub.w $w31, $w26, $w1 # encoding: [0x78,0x41,0xd7,0xdb] +# CHECK: fsub.d $w19, $w17, $w27 # encoding: [0x78,0x7b,0x8c,0xdb] +# CHECK: fsueq.w $w16, $w24, $w25 # encoding: [0x7a,0xd9,0xc4,0x1a] +# CHECK: fsueq.d $w18, $w14, $w14 # encoding: [0x7a,0xee,0x74,0x9a] +# CHECK: fsule.w $w23, $w30, $w13 # encoding: [0x7b,0xcd,0xf5,0xda] +# CHECK: fsule.d $w2, $w11, $w26 # encoding: [0x7b,0xfa,0x58,0x9a] +# CHECK: fsult.w $w11, $w26, $w22 # encoding: [0x7b,0x56,0xd2,0xda] +# CHECK: fsult.d $w6, $w23, $w30 # encoding: [0x7b,0x7e,0xb9,0x9a] +# CHECK: fsun.w $w3, $w18, $w28 # encoding: [0x7a,0x5c,0x90,0xda] +# CHECK: fsun.d $w18, $w11, $w19 # encoding: [0x7a,0x73,0x5c,0x9a] +# CHECK: fsune.w $w16, $w31, $w2 # encoding: [0x7a,0x82,0xfc,0x1c] +# CHECK: fsune.d $w3, $w26, $w17 # encoding: [0x7a,0xb1,0xd0,0xdc] +# CHECK: ftq.h $w16, $w4, $w24 # encoding: [0x7a,0x98,0x24,0x1b] +# CHECK: ftq.w $w5, $w5, $w25 # encoding: [0x7a,0xb9,0x29,0x5b] +# CHECK: madd_q.h $w16, $w20, $w10 # encoding: [0x79,0x4a,0xa4,0x1c] +# CHECK: madd_q.w $w28, $w2, $w9 # encoding: [0x79,0x69,0x17,0x1c] +# CHECK: maddr_q.h $w8, $w18, $w9 # encoding: [0x7b,0x49,0x92,0x1c] +# CHECK: maddr_q.w $w29, $w12, $w16 # encoding: [0x7b,0x70,0x67,0x5c] +# CHECK: msub_q.h $w24, $w26, $w10 # encoding: [0x79,0x8a,0xd6,0x1c] +# CHECK: msub_q.w $w13, $w30, $w28 # encoding: [0x79,0xbc,0xf3,0x5c] +# CHECK: msubr_q.h $w12, $w21, $w11 # encoding: [0x7b,0x8b,0xab,0x1c] +# CHECK: msubr_q.w $w1, $w14, $w20 # encoding: [0x7b,0xb4,0x70,0x5c] +# CHECK: mul_q.h $w6, $w16, $w30 # encoding: [0x79,0x1e,0x81,0x9c] +# CHECK: mul_q.w $w16, $w1, $w4 # encoding: [0x79,0x24,0x0c,0x1c] +# CHECK: mulr_q.h $w6, $w20, $w19 # encoding: [0x7b,0x13,0xa1,0x9c] +# CHECK: mulr_q.w $w27, $w1, $w20 # encoding: [0x7b,0x34,0x0e,0xdc] + +# CHECKOBJDUMP: fadd.w $w28, $w19, $w28 +# CHECKOBJDUMP: fadd.d $w13, $w2, $w29 +# CHECKOBJDUMP: fcaf.w $w14, $w11, $w25 +# CHECKOBJDUMP: fcaf.d $w1, $w1, $w19 +# CHECKOBJDUMP: fceq.w $w1, $w23, $w16 +# CHECKOBJDUMP: fceq.d $w0, $w8, $w16 +# CHECKOBJDUMP: fcle.w $w16, $w9, $w24 +# CHECKOBJDUMP: fcle.d $w27, $w14, $w1 +# CHECKOBJDUMP: fclt.w $w28, $w8, $w8 +# CHECKOBJDUMP: fclt.d $w30, $w25, $w11 +# CHECKOBJDUMP: fcne.w $w2, $w18, $w23 +# CHECKOBJDUMP: fcne.d $w14, $w20, $w15 +# CHECKOBJDUMP: fcor.w $w10, $w18, $w25 +# CHECKOBJDUMP: fcor.d $w17, $w25, $w11 +# CHECKOBJDUMP: fcueq.w $w14, $w2, $w21 +# CHECKOBJDUMP: fcueq.d $w29, $w3, $w7 +# CHECKOBJDUMP: fcule.w $w17, $w5, $w3 +# CHECKOBJDUMP: fcule.d $w31, $w1, $w30 +# CHECKOBJDUMP: fcult.w $w6, $w25, $w9 +# CHECKOBJDUMP: fcult.d $w27, $w8, $w17 +# CHECKOBJDUMP: fcun.w $w4, $w20, $w8 +# CHECKOBJDUMP: fcun.d $w29, $w11, $w3 +# CHECKOBJDUMP: fcune.w $w13, $w18, $w19 +# CHECKOBJDUMP: fcune.d $w16, $w26, $w21 +# CHECKOBJDUMP: fdiv.w $w13, $w24, $w2 +# CHECKOBJDUMP: fdiv.d $w19, $w4, $w25 +# CHECKOBJDUMP: fexdo.h $w8, $w0, $w16 +# CHECKOBJDUMP: fexdo.w $w0, $w13, $w27 +# CHECKOBJDUMP: fexp2.w $w17, $w0, $w3 +# CHECKOBJDUMP: fexp2.d $w22, $w0, $w10 +# CHECKOBJDUMP: fmadd.w $w29, $w6, $w23 +# CHECKOBJDUMP: fmadd.d $w11, $w28, $w21 +# CHECKOBJDUMP: fmax.w $w0, $w23, $w13 +# CHECKOBJDUMP: fmax.d $w26, $w18, $w8 +# CHECKOBJDUMP: fmax_a.w $w10, $w16, $w10 +# CHECKOBJDUMP: fmax_a.d $w30, $w9, $w22 +# CHECKOBJDUMP: fmin.w $w24, $w1, $w30 +# CHECKOBJDUMP: fmin.d $w27, $w27, $w10 +# CHECKOBJDUMP: fmin_a.w $w10, $w29, $w20 +# CHECKOBJDUMP: fmin_a.d $w13, $w30, $w24 +# CHECKOBJDUMP: fmsub.w $w17, $w25, $w0 +# CHECKOBJDUMP: fmsub.d $w8, $w18, $w16 +# CHECKOBJDUMP: fmul.w $w3, $w15, $w15 +# CHECKOBJDUMP: fmul.d $w9, $w30, $w10 +# CHECKOBJDUMP: fsaf.w $w25, $w5, $w10 +# CHECKOBJDUMP: fsaf.d $w25, $w3, $w29 +# CHECKOBJDUMP: fseq.w $w11, $w17, $w13 +# CHECKOBJDUMP: fseq.d $w29, $w0, $w31 +# CHECKOBJDUMP: fsle.w $w30, $w31, $w31 +# CHECKOBJDUMP: fsle.d $w18, $w23, $w24 +# CHECKOBJDUMP: fslt.w $w12, $w5, $w6 +# CHECKOBJDUMP: fslt.d $w16, $w26, $w21 +# CHECKOBJDUMP: fsne.w $w30, $w1, $w12 +# CHECKOBJDUMP: fsne.d $w14, $w13, $w23 +# CHECKOBJDUMP: fsor.w $w27, $w13, $w27 +# CHECKOBJDUMP: fsor.d $w12, $w24, $w11 +# CHECKOBJDUMP: fsub.w $w31, $w26, $w1 +# CHECKOBJDUMP: fsub.d $w19, $w17, $w27 +# CHECKOBJDUMP: fsueq.w $w16, $w24, $w25 +# CHECKOBJDUMP: fsueq.d $w18, $w14, $w14 +# CHECKOBJDUMP: fsule.w $w23, $w30, $w13 +# CHECKOBJDUMP: fsule.d $w2, $w11, $w26 +# CHECKOBJDUMP: fsult.w $w11, $w26, $w22 +# CHECKOBJDUMP: fsult.d $w6, $w23, $w30 +# CHECKOBJDUMP: fsun.w $w3, $w18, $w28 +# CHECKOBJDUMP: fsun.d $w18, $w11, $w19 +# CHECKOBJDUMP: fsune.w $w16, $w31, $w2 +# CHECKOBJDUMP: fsune.d $w3, $w26, $w17 +# CHECKOBJDUMP: ftq.h $w16, $w4, $w24 +# CHECKOBJDUMP: ftq.w $w5, $w5, $w25 +# CHECKOBJDUMP: madd_q.h $w16, $w20, $w10 +# CHECKOBJDUMP: madd_q.w $w28, $w2, $w9 +# CHECKOBJDUMP: maddr_q.h $w8, $w18, $w9 +# CHECKOBJDUMP: maddr_q.w $w29, $w12, $w16 +# CHECKOBJDUMP: msub_q.h $w24, $w26, $w10 +# CHECKOBJDUMP: msub_q.w $w13, $w30, $w28 +# CHECKOBJDUMP: msubr_q.h $w12, $w21, $w11 +# CHECKOBJDUMP: msubr_q.w $w1, $w14, $w20 +# CHECKOBJDUMP: mul_q.h $w6, $w16, $w30 +# CHECKOBJDUMP: mul_q.w $w16, $w1, $w4 +# CHECKOBJDUMP: mulr_q.h $w6, $w20, $w19 +# CHECKOBJDUMP: mulr_q.w $w27, $w1, $w20 + + fadd.w $w28, $w19, $w28 + fadd.d $w13, $w2, $w29 + fcaf.w $w14, $w11, $w25 + fcaf.d $w1, $w1, $w19 + fceq.w $w1, $w23, $w16 + fceq.d $w0, $w8, $w16 + fcle.w $w16, $w9, $w24 + fcle.d $w27, $w14, $w1 + fclt.w $w28, $w8, $w8 + fclt.d $w30, $w25, $w11 + fcne.w $w2, $w18, $w23 + fcne.d $w14, $w20, $w15 + fcor.w $w10, $w18, $w25 + fcor.d $w17, $w25, $w11 + fcueq.w $w14, $w2, $w21 + fcueq.d $w29, $w3, $w7 + fcule.w $w17, $w5, $w3 + fcule.d $w31, $w1, $w30 + fcult.w $w6, $w25, $w9 + fcult.d $w27, $w8, $w17 + fcun.w $w4, $w20, $w8 + fcun.d $w29, $w11, $w3 + fcune.w $w13, $w18, $w19 + fcune.d $w16, $w26, $w21 + fdiv.w $w13, $w24, $w2 + fdiv.d $w19, $w4, $w25 + fexdo.h $w8, $w0, $w16 + fexdo.w $w0, $w13, $w27 + fexp2.w $w17, $w0, $w3 + fexp2.d $w22, $w0, $w10 + fmadd.w $w29, $w6, $w23 + fmadd.d $w11, $w28, $w21 + fmax.w $w0, $w23, $w13 + fmax.d $w26, $w18, $w8 + fmax_a.w $w10, $w16, $w10 + fmax_a.d $w30, $w9, $w22 + fmin.w $w24, $w1, $w30 + fmin.d $w27, $w27, $w10 + fmin_a.w $w10, $w29, $w20 + fmin_a.d $w13, $w30, $w24 + fmsub.w $w17, $w25, $w0 + fmsub.d $w8, $w18, $w16 + fmul.w $w3, $w15, $w15 + fmul.d $w9, $w30, $w10 + fsaf.w $w25, $w5, $w10 + fsaf.d $w25, $w3, $w29 + fseq.w $w11, $w17, $w13 + fseq.d $w29, $w0, $w31 + fsle.w $w30, $w31, $w31 + fsle.d $w18, $w23, $w24 + fslt.w $w12, $w5, $w6 + fslt.d $w16, $w26, $w21 + fsne.w $w30, $w1, $w12 + fsne.d $w14, $w13, $w23 + fsor.w $w27, $w13, $w27 + fsor.d $w12, $w24, $w11 + fsub.w $w31, $w26, $w1 + fsub.d $w19, $w17, $w27 + fsueq.w $w16, $w24, $w25 + fsueq.d $w18, $w14, $w14 + fsule.w $w23, $w30, $w13 + fsule.d $w2, $w11, $w26 + fsult.w $w11, $w26, $w22 + fsult.d $w6, $w23, $w30 + fsun.w $w3, $w18, $w28 + fsun.d $w18, $w11, $w19 + fsune.w $w16, $w31, $w2 + fsune.d $w3, $w26, $w17 + ftq.h $w16, $w4, $w24 + ftq.w $w5, $w5, $w25 + madd_q.h $w16, $w20, $w10 + madd_q.w $w28, $w2, $w9 + maddr_q.h $w8, $w18, $w9 + maddr_q.w $w29, $w12, $w16 + msub_q.h $w24, $w26, $w10 + msub_q.w $w13, $w30, $w28 + msubr_q.h $w12, $w21, $w11 + msubr_q.w $w1, $w14, $w20 + mul_q.h $w6, $w16, $w30 + mul_q.w $w16, $w1, $w4 + mulr_q.h $w6, $w20, $w19 + mulr_q.w $w27, $w1, $w20 -- 2.7.4