From cb5d0419f5517c507685577dca41c9085b7d77c4 Mon Sep 17 00:00:00 2001 From: Gaurav Jain Date: Thu, 24 Mar 2022 11:50:33 +0530 Subject: [PATCH] crypto/fsl: i.MX8: Enable Job ring driver model. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit i.MX8(QM/QXP) - added support for JR driver model. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain Signed-off-by: Horia Geantă Reviewed-by: Ye Li --- arch/arm/Kconfig | 3 ++ arch/arm/include/asm/arch-imx8/imx-regs.h | 5 +++- arch/arm/mach-imx/cmd_dek.c | 1 + arch/arm/mach-imx/imx8/Kconfig | 7 +++++ arch/arm/mach-imx/imx8/cpu.c | 18 +++++++++++- board/freescale/imx8qm_mek/spl.c | 6 ++-- board/freescale/imx8qxp_mek/spl.c | 6 ++-- drivers/crypto/fsl/Kconfig | 2 +- drivers/crypto/fsl/jr.c | 47 +++++++++++++++++++++++++++++-- include/fsl_sec.h | 12 ++++---- 10 files changed, 91 insertions(+), 16 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 79b8046..efe33a5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -853,6 +853,9 @@ config ARCH_LPC32XX config ARCH_IMX8 bool "NXP i.MX8 platform" select ARM64 + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE select DM select GPIO_EXTRA_HEADER select MACH_IMX diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h index ed6e05e..2d64b06 100644 --- a/arch/arm/include/asm/arch-imx8/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ #ifndef __ASM_ARCH_IMX8_REGS_H__ @@ -47,4 +47,7 @@ #define USB_BASE_ADDR 0x5b0d0000 #define USB_PHY0_BASE_ADDR 0x5b100000 +#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + #endif /* __ASM_ARCH_IMX8_REGS_H__ */ diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 89da89c..04c4b20 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index b43739e..f969833 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -8,6 +8,7 @@ config AHAB_BOOT config IMX8 bool + select HAS_CAAM config MU_BASE_SPL hex "MU base address used in SPL" @@ -72,6 +73,9 @@ config TARGET_IMX8QM_MEK bool "Support i.MX8QM MEK board" select BOARD_LATE_INIT select IMX8QM + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_CONGA_QMX8 bool "Support congatec conga-QMX8 board" @@ -89,6 +93,9 @@ config TARGET_IMX8QXP_MEK bool "Support i.MX8QXP MEK board" select BOARD_LATE_INIT select IMX8QXP + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL endchoice diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 359f8c7..0858ea5 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ #include @@ -91,6 +91,22 @@ static int imx8_init_mu(void *ctx, struct event *event) } EVENT_SPY(EVT_DM_POST_INIT, imx8_init_mu); +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + } + + return 0; +} +#endif + int print_bootinfo(void) { enum boot_device bt_dev = get_boot_device(); diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c index 944ba74..332a662 100644 --- a/board/freescale/imx8qm_mek/spl.c +++ b/board/freescale/imx8qm_mek/spl.c @@ -1,7 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -24,6 +24,8 @@ void spl_board_init(void) { struct udevice *dev; + uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev); + uclass_find_first_device(UCLASS_MISC, &dev); for (; dev; uclass_find_next_device(&dev)) { diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c index ae6b64f..2fa6840 100644 --- a/board/freescale/imx8qxp_mek/spl.c +++ b/board/freescale/imx8qxp_mek/spl.c @@ -1,7 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -39,6 +39,8 @@ void spl_board_init(void) { struct udevice *dev; + uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev); + uclass_find_first_device(UCLASS_MISC, &dev); for (; dev; uclass_find_next_device(&dev)) { diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 231eb00..e03fcdd 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -12,7 +12,7 @@ config FSL_CAAM config CAAM_64BIT bool - default y if PHYS_64BIT && !ARCH_IMX8M + default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8 help Select Crypto driver for 64 bits CAAM version diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 8103987..1d951cf 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "jr.h" #include "jobdesc.h" #include "desc_constr.h" @@ -113,7 +114,9 @@ static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam) static int jr_init(uint8_t sec_idx, struct caam_regs *caam) { struct jobring *jr = &caam->jr[sec_idx]; - +#if CONFIG_IS_ENABLED(OF_CONTROL) + ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu"); +#endif memset(jr, 0, sizeof(struct jobring)); jr->jq_id = caam->jrid; @@ -138,7 +141,11 @@ static int jr_init(uint8_t sec_idx, struct caam_regs *caam) memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t)); memset(jr->output_ring, 0, jr->op_size); +#if CONFIG_IS_ENABLED(OF_CONTROL) + if (!ofnode_valid(scu_node)) +#endif start_jr(caam); + jr_initregs(sec_idx, caam); return 0; @@ -673,6 +680,13 @@ int sec_init_idx(uint8_t sec_idx) caam_st.jrid = 0; caam = &caam_st; #endif +#if CONFIG_IS_ENABLED(OF_CONTROL) + ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu"); + + if (ofnode_valid(scu_node)) + goto init; +#endif + ccsr_sec_t *sec = caam->sec; uint32_t mcr = sec_in32(&sec->mcfgr); #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M) @@ -735,11 +749,18 @@ int sec_init_idx(uint8_t sec_idx) liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT; #endif #endif +#if CONFIG_IS_ENABLED(OF_CONTROL) +init: +#endif ret = jr_init(sec_idx, caam); if (ret < 0) { printf("SEC%u: initialization failed\n", sec_idx); return -1; } +#if CONFIG_IS_ENABLED(OF_CONTROL) + if (ofnode_valid(scu_node)) + return ret; +#endif #ifdef CONFIG_FSL_CORENET ret = sec_config_pamu_table(liodn_ns, liodn_s); @@ -773,6 +794,23 @@ int sec_init(void) } #if CONFIG_IS_ENABLED(DM) +static int jr_power_on(ofnode node) +{ +#if CONFIG_IS_ENABLED(POWER_DOMAIN) + struct udevice __maybe_unused jr_dev; + struct power_domain pd; + + dev_set_ofnode(&jr_dev, node); + + /* Power on Job Ring before access it */ + if (!power_domain_get(&jr_dev, &pd)) { + if (power_domain_on(&pd)) + return -EINVAL; + } +#endif + return 0; +} + static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf) { if (request != CAAM_JR_RUN_DESC) @@ -785,7 +823,7 @@ static int caam_jr_probe(struct udevice *dev) { struct caam_regs *caam = dev_get_priv(dev); fdt_addr_t addr; - ofnode node; + ofnode node, scu_node; unsigned int jr_node = 0; caam_dev = dev; @@ -810,6 +848,11 @@ static int caam_jr_probe(struct udevice *dev) jr_node = jr_node >> 4; caam->jrid = jr_node - 1; + scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu"); + if (ofnode_valid(scu_node)) { + if (jr_power_on(node)) + return -EINVAL; + } break; } } diff --git a/include/fsl_sec.h b/include/fsl_sec.h index c412169..7b6e3e2 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -3,7 +3,7 @@ * Common internal memory map for some Freescale SoCs * * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ #ifndef __FSL_SEC_H @@ -194,12 +194,10 @@ typedef struct ccsr_sec { #define SEC_CHAVID_LS_RNG_SHIFT 16 #define SEC_CHAVID_RNG_LS_MASK 0x000f0000 -#define CONFIG_JRSTARTR_JR0 0x00000001 - struct jr_regs { #if defined(CONFIG_SYS_FSL_SEC_LE) && \ !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)) u32 irba_l; u32 irba_h; #else @@ -214,7 +212,7 @@ struct jr_regs { u32 irja; #if defined(CONFIG_SYS_FSL_SEC_LE) && \ !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)) u32 orba_l; u32 orba_h; #else @@ -248,7 +246,7 @@ struct jr_regs { struct sg_entry { #if defined(CONFIG_SYS_FSL_SEC_LE) && \ !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)) uint32_t addr_lo; /* Memory Address - lo */ uint32_t addr_hi; /* Memory Address of start of buffer - hi */ #else @@ -268,7 +266,7 @@ struct sg_entry { }; #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) /* Job Ring Base Address */ #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) /* Secure Memory Offset varies accross versions */ -- 2.7.4