From cae9425a3c4a2af6a306c1aa5c8acfd27136f3fc Mon Sep 17 00:00:00 2001 From: QingShan Zhang Date: Thu, 20 Sep 2018 03:09:15 +0000 Subject: [PATCH] [PowerPC] Fix the assert of combineBVOfConsecutiveLoads when element num is 1 Building a vector out of multiple loads can be converted to a load of the vector type if the loads are consecutive. But the special condition is that the element number is 1, such as <1 x i128>. So just early exit to fix the assert. Patch By: wuzish (Zixuan Wu) Differential Revision: https://reviews.llvm.org/D52072 llvm-svn: 342611 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 3 ++- llvm/test/CodeGen/PowerPC/crash.ll | 17 +++++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index dba69a1..1e51393 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -11901,7 +11901,8 @@ static SDValue combineBVOfConsecutiveLoads(SDNode *N, SelectionDAG &DAG) { IsRoundOfExtLoad = LD->getExtensionType() == ISD::EXTLOAD; } // Not a build vector of (possibly fp_rounded) loads. - if (!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD) + if ((!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD) || + N->getNumOperands() == 1) return SDValue(); for (int i = 1, e = N->getNumOperands(); i < e; ++i) { diff --git a/llvm/test/CodeGen/PowerPC/crash.ll b/llvm/test/CodeGen/PowerPC/crash.ll index 87767c6..9e2e85c 100644 --- a/llvm/test/CodeGen/PowerPC/crash.ll +++ b/llvm/test/CodeGen/PowerPC/crash.ll @@ -15,3 +15,20 @@ if.end: store i8 %bf.set, i8* %x3, align 4 ret void } + +; A BUILD_VECTOR of 1 element caused a crash in combineBVOfConsecutiveLoads() +; Test that this is no longer the case +define signext i32 @test2() { +entry: + %retval = alloca i32, align 4 + %__a = alloca i128, align 16 + %b = alloca i64, align 8 + store i32 0, i32* %retval, align 4 + %0 = load i128, i128* %__a, align 16 + %splat.splatinsert = insertelement <1 x i128> undef, i128 %0, i32 0 + %splat.splat = shufflevector <1 x i128> %splat.splatinsert, <1 x i128> undef, <1 x i32> zeroinitializer + %1 = bitcast <1 x i128> %splat.splat to <2 x i64> + %2 = extractelement <2 x i64> %1, i32 0 + store i64 %2, i64* %b, align 8 + ret i32 0 +} -- 2.7.4